AD9173 datasheet(47/144 Pages) AD

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Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

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Rev. C | 47 of 144

JESD204B ERROR MONITORING

Disparity, Not in Table, and Unexpected Control

(K) Character Errors

As per Section 7.6 of the JESD204B specification, the AD9173 can

detect disparity errors, not in table (NIT) errors, and unexpected

control character errors, and can optionally issue a sync request

and reinitialize the link when errors occur.

Several other interpretations of the JESD204B specification are

noted in this section. When three NIT errors are injected to one lane

and QUAL_RDERR (Register 0x476, Bit 4) = 1, the readback val-

ues of the bad disparity error (BDE) count register is 1. Reporting of

disparity errors that occur at the same character position of an NIT

error is disabled. No such disabling is performed for the disparity

errors in the characters after an NIT error. Therefore, it is expected

behavior that an NIT error may result in a BDE error.

Checking Error Counts

The error count can be checked for disparity errors, NIT errors,

and unexpected control character errors. The error counts are on a

per lane and per error type basis. Each error type and lane has a

must be performed:

1. Choose and enable which errors to monitor by selecting them in

ed K (UEK) character, BDE, and NIT error monitoring can be

selected for each lane by writing a 1 to the appropriate bit, as

described in Table 60. These bits are enabled by default.

2. The corresponding error counter reset bits are in Regis-

ter 0x480, Bits[2:0] to Register 0x487, Bits[2:0]. Write a 1 to

the corresponding bit to reset that error counter.

3. Registers 0x488, Bits[2:0] to Register 0x48F, Bits[2:0] have the

terminal count hold indicator for each error counter. If this flag

is enabled, when the terminal error count of 0xFF is reached,

the counter ceases counting and holds that value until reset.

Otherwise, it wraps to 0x00 and continues counting. Select the

desired behavior and program the corresponding register bits

per lane.

Check for Error Count Over Threshold

To check for the error count over threshold, follow these steps:

1. Define the error counter threshold. The error counter threshold

can be set to a user defined value in Register 0x47C, or

left to the default value of 0xFF. When the error threshold is

reached, an IRQ is generated, SYNCOUTx± is asserted, or

both, depending on the mask register settings. This one error

threshold is used for all three types of errors (UEK, NIT, and

BDE).

2. Set the SYNC_ASSERT_MASK bits. The SYNCOUTx± asser-

tion behavior is set in Register 0x47D, Bits[2:0]. By default,

when any error counter of any lane is equal to the threshold,

it asserts SYNCOUTx± (Register 0x47D, Bits[2:0] = 0b111).

When setting the SYNC_ASSERT_MASK bits, LINK_PAGE

(Register 0x300, Bit 2) must be set to 1.

3. Read the error count reached indicator. Each error counter

has a terminal count reached indicator, per lane. This indicator

is set to 1 when the terminal count of an error counter for

a particular lane is reached. These status bits are located in

be read back to indicate whether a particular lane is active.

Error Counter and IRQ Control

For error counter and IRQ control, follow these steps:

1. Enable the interrupts. Enable the JESD204B interrupts. The

interrupts for the UEK, NIT, and BDE error counters are in

when bringing up the link, such as lane deskewing, initial lane

sync, good check sum, frame sync, code group sync (Register

0x4B8, Bits[4:0], and configuration mismatch (Register 0x4B9,

Bit 0). These bits are off by default but can be enabled by

writing 0b1 to the corresponding bit.

2. Read the JESD204B interrupt status. The interrupt status bits

are in Register 0x4BA, Bits[7:0] and Register 0x4BB, Bit 0, with

the status bit position corresponding to the enable bit position.

3. It is recommended to enable all interrupts that are planned to

be used prior to bringing up the JESD204B link. When the link

is up, the interrupts can be reset and then used to monitor the

link status.

Monitoring Errors via SYNCOUTx±

When one or more disparity, NIT, or unexpected control character

errors occur, the error is reported on the SYNCOUTx± pin as

per Section 7.6 of the JESD204B specification. The JESD204B

specification states that the SYNCOUTx± signal is asserted for

exactly two frame periods when an error occurs. For the AD9173,

the width of the SYNCOUTx± pulse can be programmed to ½, 1, or

2 PCLK cycles. The settings to achieve a SYNCOUTx± pulse of two

frame clock cycles are given in Table 32.

Table 32. Setting SYNCOUTx± Error Pulse Duration

PCLK Factor (Frames/

PCLK)

SYNC_ERR_DUR (Register 0x312,

Bits[7:4]) Setting1

0 (default)

1.5

0.5

1 These register settings assert the SYNCOUTx± signal for two frame clock

cycle pulse widths.

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