AD9173 datasheet(34/144 Pages) AD

34 / 144 page

Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

analog.com

Rev. C | 34 of 144

PHYSICAL LAYER

The physical layer of the JESD204B interface, hereafter referred

to as the deserializer, has eight identical channels. Each channel

consists of the termination, an equalizer, a clock and data recovery

(CDR) circuit, and the 1:40 demux function (see Figure 49).

Figure 49. Deserializer Block Diagram

JESD204B data is input to the AD9173 via the SERDINx± differen-

tial input pins, per the JESD204B specification.

Interface Power-Up and Input Termination

Before using the JESD204B interface, it must be powered up by

setting Register 0x200, Bit 0 = 0. In addition, each physical lane

(PHY) that is not being used (SERDINx±) must be powered down.

To do so, set the corresponding Bit x for Physical Lane x in

is not being used.

The AD9173 autocalibrates the input termination to 50 Ω. This

calibration routine is performed automatically when the JESD204B

interface blocks are configured and does not require any additional

SPI register writes.

Receiver Eye Mask

The AD9173 is compatible with the JESD204B specification regard-

ing the receiver eye mask and is capable of capturing data that

complies with the mask in Figure 50. Figure 50 shows the receiver

eye normalized to the data rate interval. The AD9173 also supports

an increased insertion loss limit, as defined in the Equalization

section.

Figure 50. Receiver Eye Mask

Clock Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks can

be derived from the following equations:

Data Rate = DAC Rate/Total Interpolation

Lane Rate = (M/L) × NP × (10/8) × Data Rate

Byte Rate = Lane Rate/10

This relationship comes from 8-bit/10-bit encoding, where each byte

is represented by 10 bits.

PCLK Rate = Byte Rate/4

Figure 51. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block

AD9173 Datasheet(PDF) 34 Page - Analog Devices

AD9173 Datasheet(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL