AD9173 datasheet(63/144 Pages) AD

63 / 144 page

Data Sheet

AD9173

APPLICATIONS INFORMATION

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Rev. C | 63 of 144

SYNCOUT±, SYSREF±, and CLK± Signals

The SYSREF± signal on the AD9173 is a low speed, LVDS,

differential signal. The SYNCOUTx± signals are LVDS or CMOS se-

lectable. When LVDS mode is selected, use controlled impedance

traces routed as 100 Ω differential impedance and 50 Ω to ground

when routing these signals. As with the SERDIN0± to SERDIN7±

data pairs, it is important to keep these signals separated from

potential noise sources, such as high speed digital signals and

noisy supplies. Separate the SYNCOUTx± signal from other noisy

signals because noise on the SYNCOUTx± may be interpreted as

a request for /K/ characters. It is important to keep similar trace

lengths for the CLK± and SYSREF± signals from the clock source

to each of the devices on either end of the JESD204B links (see

Figure 85). If using a clock chip that can tightly control the phase

of CLK± and SYSREF±, the trace length matching requirements are

greatly reduced. The AD9516-0, ADCLK925, and HMC7044 are a

few examples of possible clocking solutions depending on system

requirements.

Figure 85. SYSREF± Signal and Device Clock Trace Length

AD9173 Datasheet(PDF) 63 Page - Analog Devices