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Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

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Rev. C | 41 of 144

Link Delay

The link delay of a JESD204B system is the sum of the fixed

and variable delays from the transmitter, channel, and receiver as

shown in Figure 59.

For proper functioning, all lanes on a link must be read during

the same LMFC period. Section 6.1 of the JESD204B specification

states that the LMFC period must be larger than the maximum link

delay. For the AD9173, this is not necessarily the case; instead,

the AD9173 use a local LMFC for each link (LMFCRx) that can be

delayed from the SYSREF± aligned LMFC. Because the LMFC is

periodic, this delay can account for any amount of fixed delay. As a

result, the LMFC period must only be larger than the variation in the

link delays, and the AD9173 can achieve proper performance with

a smaller total latency. Figure 60 and Figure 61 show a case where

the link delay is greater than an LMFC period. Note that it can be

accommodated by delaying LMFCRx.

Figure 60. Link Delay > LMFC Period Example

Figure 61. LMFC_DELAY_x to Compensate for Link Delay > LMFC

The method to select the LMFCDel (Register 0x304) and LMFCVar

(Register 0x306) variables is described in the Link Delay Setup

Example, With Known Delays section and the Link Delay Setup

Example, Without Known Delay section. Note that the setting for

LMFCDel must not equal or exceed the number of PCLK cycles per

LMFC period in the current mode.

Similarly, LMFCVar must not exceed the number of PCLK cycles

per LMFC period in the current mode or be set to <12 (whichever

value is smaller).

Setting LMFCDel appropriately ensures that all the corresponding

data samples arrive in the same LMFC period. Then, LMFCVar is

written into the receive buffer delay (RBD) to absorb all link delay

variation. This write ensures that all data samples arrived before

reading. By setting these to fixed values across runs and devices,

deterministic latency is achieved.

The RBD described in the JESD204B specification takes values

from one frame clock cycle to /K/ frame clock cycles, and the RBD

of the AD9173 takes values from 0 PCLK cycle to 12 PCLK cycles.

As a result, up to 12 PCLK cycles of total delay variation can be

absorbed. LMFCVar and LMFCDel are both in PCLK cycles. The

PCLK factor, or number of frame clock cycles per PCLK cycle, is

equal to 4/f. For more information on this relationship, see the Clock

Relationships section.

Two examples follow that show how to determine LMFCVar and

LMFCDel. After they are calculated, write LMFCDel into Register

0x304 for all devices in the system, and write LMFCVar to Register

0x306 for all devices in the system.

Figure 62. LMFC Delay Calculation Example

AD9173 Datasheet(PDF) 41 Page - Analog Devices

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