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AD9173 Datasheet(PDF) 67 Page - Analog Devices |
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AD9173 Datasheet(HTML) 67 Page - Analog Devices |
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67 / 144 page  Data Sheet AD9173 START-UP SEQUENCE analog.com Rev. C | 67 of 144 Several steps are required to program the AD9173 to the proper operating state after the device is powered up. This sequence is divided into several steps, and is listed in Table 49 to Table 58, along with an explanation of the purpose of each step. Private registers are reserved but must be written for proper operation. Blank cells or cells with a variable or bit field name (in all capital letters) in Table 49 to Table 58 indicate that the value depends on the result as described in the Description column. Table 49. Power-Up and Required Register Writes R/W Register Bits Value Description W 0x000 [7:0] 0x81 Soft reset. W 0x000 [7:0] 0x3C Release reset and set to 4-wire SPI (optional; leave at the default of the 3-wire SPI). W 0x091 [7:0] 0x00 Power up clock receiver. W 0x206 [7:0] 0x01 Take PHYs out of reset. W 0x705 [7:0] 0x01 Enable boot loader. Pause Wait 1 ms. W 0x090 [7:0] 0x00 Power on DACs and bias circuitry. Table 50. DAC PLL Configuration R/W Register Bits Value Description W 0x095 [7:0] 0x00 or 0x01 Bypass PLL. Set to 0x00 to use internal DAC PLL. If the user plans to supply the DAC clock directly, set this register to 0x01 and execute the following two register writes; then, skip the remaining writes in this table. W 0x790 [7:0] 0xFF or 0x00 Write this register to 0xFF if bypassing the PLL (Register 0x095 = 0x01). If using the PLL, write this register to 0x00. W 0x791 [7:0] 0x1F or 0x00 Write this register to 0xFF if bypassing the PLL (Register 0x095 = 0x01) and then skip the remaining register writes in this table and continue to Table 51. If using the PLL, write this register to 0x00 as well as the remainder of the register writes in this table. W 0x796 [7:0] 0xE5 DAC PLL required write. W 0x7A0 [7:0] 0xBC DAC PLL required write. W 0x794 [5:0] DACPLL_CP Set DAC PLL charge pump current. The recommended setting is 0x08, but can range from 0x04 to 0x10 for different phase noise performance targets. W 0x797 [7:0] 0x10 DAC PLL required write. W 0x797 [7:0] 0x20 DAC PLL required write. W 0x798 [7:0] 0x10 DAC PLL required write. W 0x7A2 [7:0] 0x7F DAC PLL required write. Pause Wait 100 ms. W 0x799 DAC PLL divider settings. [7:6] ADC_CLK_DIVIDER ADC driver/clock output divide ratio. 0b00 = ÷1. 0b01 = ÷2. 0b10 = ÷3. 0b11 = ÷4. [5:0] N_DIVIDER Programmable N divider. N_DIVIDER = (fDAC × M_DIVIDER)/(8 × reference clock). W 0x793 DAC PLL divider settings. [7:2] 0x06 Keep default value for these bits. [1:0] M_DIVIDER-1 Programmable predivider M_DIVIDER-1 (in n − 1 notation). The relevant calculation is as follows: PFD Frequency = reference clock/M_DIVIDER, where 25 MHz ≤ PFD frequency ≤ 770 MHz. If 9.96 GHz ≤ PLL VCO frequency ≤ 10.87 GHz, must keep 25 MHz ≤ PFD frequency ≤ 225 MHz. 0b00 = ÷1. 0b01 = ÷2. 0b10 = ÷3. 0b11 = ÷4. W 0x094 [7:2] 0x00 Keep default value for these bits. 1 PLL_VCO_DIV3_EN Enable PLL output clock to be divided by 3. If this bit is set to 1, DAC clock = PLL VCO frequency/3. |
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