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AD9173 Datasheet(PDF) 70 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 70 Page - Analog Devices

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Data Sheet
AD9173
START-UP SEQUENCE
analog.com
Rev. C | 70 of 144
Table 54. Channel Datapath Setup: Digital Gain and Channel NCOs
R/W
Register
Bits
Value
Description
0b0 = upper sideband.
0b1 = lower sideband (spectral flip).
0
If dc test mode or NCO test mode is desired, set this bit to 1 to enable the test tone generation. Otherwise, set this bit to the
default value of 0.
Integer NCO mode calculation: DDSC_FTW = (fCARRIER/fNCO) × 248, where fNCO = fDATA/CH_INTERP_MODE.
W
0x132
[7:0]
Write DDSC_FTW[7:0].
W
0x133
[7:0]
Write DDSC_FTW[15:8].
W
0x134
[7:0]
Write DDSC_FTW[23:16].
W
0x135
[7:0]
Write DDSC_FTW[31:24].
W
0x136
[7:0]
Write DDSC_FTW[39:32].
W
0x137
[7:0]
Write DDSC_FTW[47:40].
W
0x138
[7:0]
Write DDSC_NCO_PHASE_OFFSET[7:0]. Calculation: DDSC_NCO_PHASE_OFFSET = (Degrees Offset/180) × 215.
W
0x139
[7:0]
Write DDSC_NCO_PHASE_OFFSET[15:8].
If using NCO modulus mode, also program modulus parameters. If not, skip this section. For modulus NCO mode: (fCARRIER/
fNCO) = (X + (A/B))/248 where DDSC_ACC_DELTA = A, DDSC_ACC_MODULUS = B, and DDSC_FTW = X.
W
0x13A
[7:0]
Write DDSC_ACC_MODULUS[7:0].
W
0x13B
[7:0]
Write DDSC_ACC_MODULUS[15:8].
W
0x13C
[7:0]
Write DDSC_ACC_MODULUS[23:16].
W
0x13D
[7:0]
Write DDSC_ACC_MODULUS[31:24].
W
0x13E
[7:0]
Write DDSC_ACC_MODULUS[39:32].
W
0x13F
[7:0]
Write DDSC_ACC_MODULUS[47:40].
W
0x140
[7:0]
Write DDSC_ACC_DELTA[7:0].
W
0x141
[7:0]
Write DDSC_ACC_DELTA[15:8].
W
0x142
[7:0]
Write DDSC_ACC_DELTA[23:16].
W
0x143
[7:0]
Write DDSC_ACC_DELTA[31:24].
W
0x144
[7:0]
Write DDSC_ACC_DELTA[39:32].
W
0x145
[7:0]
Write DDSC_ACC_DELTA[47:40].
W
0x131
0
0b1
Update all NCO phase and FTW words.
Table 55 lists optional registers to configure the main DAC datapaths if they are being configured for a specific application. If the main DAC
datapaths are bypassed (DP_INTERP_MODE = 1 for 1× channel interpolation), Table 55 can be skipped in the start-up sequence.
Table 55. Main DAC Datapath Setup: PA Protect and Main NCOs
R/W
Register
Bits
Value
Description
W
0x008
[7:6]
MAINDAC_PAGE. Select the main DAC datapath to be programmed at the same time (or repeat this block for each DAC
datapath to independently program values). Bit x of this control corresponds to the DAC x datapath.
W
0x112
3
Enable NCO for selected channels in paging Register 0x008.
0b0 = disable NCO.
0b1 = enable NCO.
2
Enable NCO modulus for selected channels in paging Register 0x008.
0b0 = disable NCO modulus.
0b1 = enable NCO modulus.
1
Select sideband from modulation result.
0b0 = upper sideband.
0b1 = lower sideband (spectral flip).
0
Set this bit to 0.
Integer NCO mode calculation: DDSM_FTW = (fCARRIER/fDAC) × 248.
W
0x114
[7:0]
Write DDSM_FTW[7:0].



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