AD9173 datasheet(52/144 Pages) AD

52 / 144 page

Data Sheet

AD9173

DIGITAL DATAPATH

analog.com

Rev. C | 52 of 144

nel half-band cascaded configuration is shown in Figure 70, with

each of the useable bandwidths of the channel interpolation filters

listed in Table 37.

Figure 70. Channel Interpolation Half-Band Filter Block Diagram

Table 37. Channel Interpolation Useable Bandwidths and Rejection

Half-Band Filter

Bandwidth

(×fIN_FILTER1) (%)

Stop Band Rejection (dB)

HB0

TB0

HB1

HB2

1 fIN_FILTER is the frequency at the input of the half-band filter.

Channel Digital Modulation

The AD9173 has digital modulation features to modulate the base-

band quadrature signal to a desired frequency. There are two

stages of complex digital modulation available in the AD9173:

channel modulation and main modulation. Each main DAC has

three channels, each with its own NCO, that can individually mod-

ulate the data from each channel with a unique frequency and

phase offset. The AD9173 is equipped with several NCO modes.

The default NCO is a 48-bit, integer NCO. There is an additional

modulus option for each channel NCO where the A/B ratio of the

dual modulus NCO allows the output frequency to be synthesized

with very fine precision. NCO mode is selected as shown in Table

38. These controls are paged per the channel page masks in the

CHANNEL_PAGE bits (Register 0x008, Bits[5:0]).

Table 38. Channel Modulation Mode Selection

Modulation Mode

Modulation Type

None

0b0

48-Bit Integer NCO

0b1

0b0

48-Bit Dual Modulus NCO

0b1

The channel NCO blocks also contain sideband selection controls

as well as options for how the FTW and phase offset controls are

updated.

Calculate the phase offset word control as follows:

−180° ≤ Degrees Offset ≤ +180°

Degrees Offset = 180° × (DDSC_NCO_PHASE_OFFSET/215)

where DDSC_NCO_PHASE_OFFSET is a 16-bit twos complement

value programmed in the registers listed in Table 39.

Table 39. Channel NCO Phase Offset Registers

Address

Value

Description

0x138

DDSC_NCO_PHASE_OFFSET[7:0]

8 LSBs of phase offset

0x139

DDSC_NCO_PHASE_OFFSET[15:8] 8 MSBs of phase offset

48-Bit Dual Modulus NCO

The 48-bit dual modulation mode uses an NCO, a phase shifter,

and a complex modulator to modulate the signal by a programma-

ble carrier signal, as shown in Figure 71. This configuration allows

output signals to be placed anywhere in the output spectrum up to

±fNCO/2 with very fine frequency resolution.

The NCO produces a quadrature carrier to translate the input

signal to a new center frequency. A quadrature carrier is a pair of

sinusoidal waveforms of the same frequency, offset 90° from each

other. The frequency of the quadrature carrier is set via a FTW. The

quadrature carrier is mixed with the I and Q data and then summed

into the I and Q datapaths, as shown in Figure 71.

Integer NCO Mode

The channel 48-bit NCOs can be used as integer NCOs. The

FTW for the channel NCOs depends on the speed at which the

channel NCO block is running (fNCO), which is the same rate as the

summing node (maximum of 1.54 GSPS) and can be calculated by

using the following formulas:

fNCO = fDATA × Channel Interpolation

fNCO = fDAC/Main Interpolation = fSUMMING_NODE

The FTWs for each individual channel can be programmed sepa-

rately and are calculated by using the following formula:

−fNCO/2 ≤ fCARRIER < +fNCO/2

DDSC_FTW = (fCARRIER/fNCO) × 248

where DDSC_FTW is a 48-bit, twos complement number.

The frequency tuning word is set as shown in Table 40.

Table 40. Channel NCO FTW Registers

Address

Value

Description

0x132

DDSC_FTW[7:0]

8 LSBs of FTW

0x133

DDSC_FTW[15:8]

Next 8 bits of FTW

0x134

DDSC_FTW[23:16]

Next 8 bits of FTW

0x135

DDSC_FTW[31:24]

Next 8 bits of FTW

0x136

DDSC_FTW[39:32]

Next 8 bits of FTW

0x137

DDSC_FTW[47:40]

8 MSBs of FTW

Unlike other registers, the FTW registers are not updated immedi-

ately upon writing. Instead, the FTW registers update on the rising

edge of DDSC_FTW_LOAD_REQ (Register 0x131, Bit 0). After an

update request, DDSC_FTW_LOAD_ACK (Register 0x131, Bit 1)

must be high to acknowledge that the FTW has updated.

AD9173 Datasheet(PDF) 52 Page - Analog Devices

AD9173 Datasheet(HTML) 52 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL