AD9173 datasheet(9/144 Pages) AD

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Data Sheet

AD9173

SPECIFICATIONS

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Rev. C | 9 of 144

Table 5.

Parameter

Symbol

Test Comments/Conditions

Min

Typ

Max

Unit

Current Output

High

IOH

Low

IOL

INTERRUPT OUTPUTS (IRQ0, IRQ1)

Voltage Output

High

VOH

1.71

Low

VOL

0.075

DIGITAL INPUT DATA TIMING SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise noted.

For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C.

Table 6.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LATENCY1

Channel Interpolation Factor, Main

Datapath Interpolation Factor

LMFC_VAR_x = 12, LMFC_DELAY_x = 12, unless otherwise noted

1×, 1×2

JESD204B Mode 153

420

DAC clock cycle

JESD204B Mode 16

440

DAC clock cycle

JESD204B Mode 17

590

DAC clock cycle

1×, 8×2

JESD204B Mode 3

1390

DAC clock cycle

JESD204B Mode 83

1820

DAC clock cycle

JESD204B Mode 9

1920

DAC clock cycle

1×, 12×2

JESD204B Mode 83

2700

DAC clock cycle

JESD204B Mode 9

2840

DAC clock cycle

2×, 6×2

JESD204B Mode 3, Mode 4

1970

DAC clock cycle

JESD204B Mode 5

1770

DAC clock cycle

2×, 8×2

JESD204B Mode 0

2020

DAC clock cycle

JESD204B Mode 3, Mode 4

2500

DAC clock cycle

3×, 6×2

JESD204B Mode 3, Mode 4

2880

DAC clock cycle

JESD204B Mode 5, Mode 6

2630

DAC clock cycle

3×, 8×2

JESD204B Mode 3, Mode 4

3310

DAC clock cycle

JESD204B Mode 5, Mode 6

2980

DAC clock cycle

4×, 6×2

JESD204B Mode 0, Mode 1, Mode 2

2410

DAC clock cycle

4×, 8×2

JESD204B Mode 0, Mode 1, Mode 2

3090

DAC clock cycle

6×, 6×2

JESD204B Mode 0, Mode 1, Mode 2

3190

DAC clock cycle

6×, 8×2

JESD204B Mode 0, Mode 1, Mode 2

4130

DAC clock cycle

8×, 6×2

JESD204B Mode 7

3300

DAC clock cycle

8×, 8×2

JESD204B Mode 7

4270

DAC clock cycle

DETERMINISTIC LATENCY

Fixed

PCLK4

Variable

PCLK cycles

SYSREF± TO LOCAL MULTIFRAME CLOCK

(LMFC) DELAY

DAC clock cycles

1 Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay.

2 The first value listed in this specification is the channel interpolation factor, and the second value is the main datapath interpolation factor.

3 LMFC_VAR_x = 7 and LMFC_DELAY_x = 4

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