AD9173 datasheet(60/144 Pages) AD

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Data Sheet

AD9173

INTERRUPT REQUEST OPERATION

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The AD9173 provides an interrupt request output signal (IRQ) on

Ball D9 (IRQ0) and Ball E9 (IRQ1) that can be used to notify an

external host processor of significant device events. The IRQ output

can be switched between the IRQ0 pin or the IRQ1 pin by setting

the corresponding bit for the IRQ signal in Register 0x028, Regis-

ter 0x029, Register 0x02A, and Register 0x02B. Upon assertion of

the interrupt, query the device to determine the precise event that

occurred. The IRQx pins are open-drain, active low outputs. Pull the

IRQx pins high, external to the device. These pins can be tied to the

interrupt pins of other devices with open-drain outputs to wire; OR

these pins together.

Figure 81 shows a simplified block diagram of how the IRQx

blocks works. If IRQ_EN is low, the INTERRUPT_SOURCE sig-

nal is set to 0. If IRQ_EN is high, any rising edge of EVENT

causes the INTERRUPT_SOURCE signal to be set high. If any

INTERRUPT_SOURCE signal is high, the IRQx pin is pulled low.

INTERRUPT_SOURCE can be reset to 0 by either an IRQ_RESET

signal or a DEVICE_RESET signal.

Depending on the STATUS_MODE signal, EVENT_STATUS reads

back an event signal or an INTERRUPT_SOURCE signal. The

AD9173 has several IRQ register blocks that can monitor up to 86

events, depending on the device configuration. Certain details vary

by IRQ register block, as described in Table 47. Table 48 shows the

source registers of the IRQ_EN, IRQ_RESET, and STATUS_MODE

signals in Figure 81, as well as the address where EVENT_STA-

TUS is read back.

Table 47. IRQ Register Block Details

Event Reported EVENT_STATUS

0x020 to 0x27

Per chip

INTERRUPT_SOURCE if IRQ is

enabled; if not, it is an event

0x4B8 to 0x4BB; 0x470

to 0x473

Per link and lane INTERRUPT_SOURCE if IRQ is

enabled; if not, 0

INTERRUPT SERVICE ROUTINE

Interrupt request management starts by selecting the set of event

flags that require host intervention or monitoring. Enable the events

that require host action so that the host is notified when they occur.

For events requiring host intervention upon IRQ activation, run the

following routine to clear an interrupt request:

1. Read the status of the event flag bits that are being monitored.

2. Disable the interrupt by writing 0 to IRQ_EN.

3. Read the event source.

4. Perform any actions that may be required to clear the cause of

the event. In many cases, no specific actions may be required.

5. Verify that the event source is functioning as expected.

6. Clear the interrupt by writing 1 to IRQ_RESET.

7. Enable the interrupt by writing 1 to IRQ_EN.

Figure 81. Simplified Schematic of IRQx Circuitry

Table 48. IRQ Register Block Address of IRQ Signal Details

Block

Address of IRQ Signals1

IRQ_EN

IRQ_RESET

STATUS_MODE

EVENT_STATUS

0x020 to

0x023

0x020 to 0x023; R/W per chip

0x024 to 0x027; per chip

STATUS_MODE= IRQ_EN

0x024 to 0x027; R per chip

0x4B8 to

0x4BB

0x4B8, 0x4B9; W per error type

0x4BA, 0x4BB; W per error type

Not applicable, STATUS_MODE = 1

0x4BA, 0x4BB; W per chip

0x470 to

0x473

0x470 to 0x473; W per error type

0x470 to 0x473; W per link

Not applicable, STATUS_MODE = 1

0x470 to 0x473; W per link

1 R is read, W is write, and R/W is read/write.

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