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Data Sheet

AD9173

DIGITAL DATAPATH

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Rev. C | 53 of 144

The DDSC_SEL_SIDEBAND bit (Register 0x130, Bit 1 = 0b1) is a

convenience bit that can be set to use the lower sideband modula-

tion result, which is equivalent to flipping the sign of the FTW.

Figure 71. NCO Modulator Block Diagram

Channel Modulus NCO Mode (Direct Digital

Synthesis (DDS))

Each of the channel 48-bit NCOs can also be used in a dual

modulus mode to create fractional frequencies beyond the 48-bit

accuracy. The modulus mode is enabled by programming the

DDSC_MODULUS_EN bit in the DDSC_DATAPATH_CFG register

to 1 (Register 0x130, Bit 2 = 0b1).

The frequency ratio for the programmable modulus direct digital

synthesis (DDS) is very similar to that of the typical accumulator-

based DDS. The only difference is that N is not required to be

a power of two for the programmable modulus, but can be an

arbitrary integer. In practice, hardware constraints place limits on

the range of values for N. As a result, the modulus extends the

use of the NCO to applications that require exact rational frequency

synthesis. The underlying function of the programmable modulus

technique is to alter the accumulator modulus.

Implementation of the programmable modulus function within the

AD9173 is such that the fraction, M/N, is expressible by the

following equation. Note that the form of the equation implies a

compound frequency tuning word with X representing the integer

part and A/B representing the fractional part.

fCARRIER

fNCO

=MN=X+AB248

where:

X is programmed in Register 0x132 to Register 0x137.

A is programmed in Register 0x140 to Register 0x145.

B is programmed in Register 0x13A to Register 0x13F.

Programmable Modulus Example

Consider the case in which fNCO = 1500 MHz and the desired

value of fCARRIER is 150 MHz. This scenario synthesizes an output

frequency that is not a power of two submultiple of the sample rate,

namely fCARRIER = (1/10) fNCO, which is not possible with a typical

accumulator-based DDS. The frequency ratio, fCARRIER/fDAC, leads

directly to M and N, which are determined by reducing the fraction

(150,000,000/1,500,000,000) to its lowest terms, that is,

M/N = 150,000,000/1,500,000,000 = 1/10

Therefore, M = 1 and N = 10.

After calculation, X = 28,147,497,671,065, A = 3, and B = 5.

Programming these values into the registers for X, A, and B

(X is programmed in Register 0x132 to Register 0x137 for DDSC_

FTWx, B is programmed in Register 0x13A to Register 0x13F for

DDSC_ACC_MODULUSx, and A is programmed in Register 0x140

to Register 0x145 for DDSC_ACC_DELTAx) causes the NCO to

produce an output frequency of exactly 150 MHz given a 1500 MHz

sampling clock. For more details, refer to the AN-953 Application

Note.

NCO Reset

Resetting the NCO can be useful when determining the start time

and phase of the NCO. The NCO can be reset by several different

methods, including a SPI write or by the SYSREF± signal.

Channel Summing Node

The channel datapaths all combine at the summing node junction

before continuing on to the main DAC datapath. The summation

of any number of channels being used must not exceed the ±215

value range to avoid clipping of the data signal into the main

datapath. The maximum data rate for each channel when the

channel interpolation is >1× is limited by the summing node junction

maximum speed of 1.54 GSPS. If the channel data-paths are

bypassed (channel interpolation is 1×), the summing node block is

also bypassed, as shown in Figure 69.

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