AD9173 datasheet(14/144 Pages) AD

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Data Sheet

AD9173

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. C | 14 of 144

Figure 2. Pin Configuration

Table 12. Pin Function Descriptions

Pin No.

Mnemonic

Description

1.0 V Supply

H3 to H5, H8 to H10, J6, M2, M11

AVDD1.0

1.0 V Clock and Analog Supplies. These pins supply the clock receivers, clock distribution, the

on-chip DAC clock multiplier, and the DAC analog core. Clean power supply rail sources are

required on these pins.

F5 to F8

DVDD1.0

1.0 V Digital Supplies. These pins supply power to the DAC digital circuitry. Clean power supply rail

sources are required on these pins.

F4, F9

DAVDD1.0

1.0 V Digital to Analog Supplies. These pins can share a supply rail with the DVDD1.0 supply

(electrically connected) but must have separate supply plane and decoupling capacitors for the

PCB layout to improve isolation for these two pins. Clean power supply rail sources are required on

these pins.

C1, C2, C5, C7, C8, C11, C12, D6

SVDD1.0

1.0 V SERDES Supplies to the JESD204B Data Interface. Clean power supply rail sources are

required on these pins.

1.8 V Supply

K3, K5, K7, K10, L3, L6, L7, L10

AVDD1.8

1.8 V Analog Supplies to the On-Chip DAC Clock Multiplier and the DAC Analog Core. Clean

power supply rail sources are required on these pins.

C6, D3, D10, E3, E10

DVDD1.8

1.8 V Digital Supplies to the JESD204B Data Interface and the Other Input/Output Circuitry, Such

as the Serial Port Interface (SPI). Clean power supply rail sources are required on these pins.

Ground

A1, A6, A7, A12, B1, B6, B7, B12, C3, C4, C9,

C10, D5, D7, F1 to F3, F10 to F12, G1 to G12,

H11, J1, J3 to J5, J8 to J11, K2, K8, K9, K11, K12,

L2, L4, L5, L8, L9, L11, M1, M3, M6, M7, M10,

M12

GND

Device Common Ground.

RF Clock

J12

CLKIN+

Positive Device Clock Input. This pin is the clock input for the on-chip DAC clock multiplier,

REFCLK, when the DAC PLL is on. This pin is also the clock input for the DAC sample clock or

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