AD9173 datasheet(38/144 Pages) AD

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Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

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Rev. C | 38 of 144

Lane First In/First Out (FIFO)

The FIFOs in front of the crossbar switch and deframer synchronize

the samples sent on the high speed serial data interface with

the deframer clock by adjusting the phase of the incoming data.

The FIFO absorbs timing variations between the data source and

the deframer; this allows up to two PCLK cycles of drift from the

transmitter. The FIFO_STATUS_REG_0 register and FIFO_STA-

TUS_REG_1 register (Register 0x30C and Register 0x30D, respec-

tively) can be monitored to identify whether the FIFOs are full or

empty.

Lane FIFO IRQ

An aggregate lane FIFO error bit is also available as an IRQ event.

Use Register 0x020, Bit 2 to enable the lane FIFO error bit, and

then use Register 0x024, Bit 2 to read back its status and reset the

IRQ signal. See the Interrupt Request Operation section for more

information.

Crossbar Switch

ical lanes (SERDINx±) to logical lanes used by the SERDES de-

framers.

Table 23. Crossbar Registers

Address

Bits

Logical Lane

0x308

[2:0]

SRC_LANE0

0x308

[5:3]

SRC_LANE1

0x309

[2:0]

SRC_LANE2

0x309

[5:3]

SRC_LANE3

0x30A

[2:0]

SRC_LANE4

0x30A

[5:3]

SRC_LANE5

0x30B

[2:0]

SRC_LANE6

0x30B

[5:3]

SRC_LANE7

Write each SRC_LANEy with the number (x) of the desired physical

lane (SERDINx±) from which to obtain data. By default, all logical

lanes use the corresponding physical lane as their data source. For

example, by default, SRC_LANE0 = 0; therefore, Logical Lane 0

obtains data from Physical Lane 0 (SERDIN0±). To use SERDIN4±

as the source for Logical Lane 0 instead, the user must write

SRC_LANE0 = 4.

Lane Inversion

be used to ease routing of the SERDINx± signals. For each Logical

Lane x, set Bit x of Register 0x334 to 1 to invert it.

Deframer

The AD9173 consists of two quad-byte deframers (QBDs) paged

by the LINK_PAGE control in Register 0x300, Bit 2. The deframer

accepts the 8-bit/10-bit encoded data from the deserializer (via the

crossbar switch), decodes it, and descrambles it into JESD204B

frames before passing it to the transport layer to be converted to

DAC samples. The deframer processes four symbols (or octets) per

processing clock (PCLK) cycle.

The deframer uses the JESD204B parameters that the user has

programmed into the register map to identify how the data is

packed, and unpacks it. The JESD204B parameters are described

in detail in the Transport Layer section; many of the parameters are

also needed in the transport layer to convert JESD204B frames into

samples.

Descrambler

The AD9173 provides an optional descrambler block using a self

synchronous descrambler with the following polynomial:

1 + x14 + x15

Enabling data scrambling reduces spectral peaks that are produced

when the same data octets repeat from frame to frame. It also

makes the spectrum data independent so that possible frequency

selective effects on the electrical interface do not cause data de-

pendent errors. Descrambling of the data is enabled by setting the

SCR bit (Register 0x453, Bit 7) to 1.

SYNCING LMFC SIGNALS

The AD9173 requires a synchronization (sync) to align the LMFC

and other internal clocks before the SERDES links are brought

online. The synchronization is a one-shot sync, where the synchro-

nization process begins on the next edge of the alignment signal

following the assertion of the SYSREF_MODE_ONESHOT control

in Register 0x03A, Bit 1.

In Subclass 1, the SYSREF± rising edge acts as the alignment

edge; in Subclass 0, an internal processing clock acts as the

alignment edge. When a sync has completed, the SYNC_ROTA-

TION_DONE (Register 0x03A, Bit 4) bit is asserted and remains

asserted until another sync is requested.

After a synchronization occurs, the JESD204B link can be enabled.

In Subclass 1, the latency of the JESD204B system is deterministic

and allows synchronization across multiple devices, if desired.

SYSREF± Signal

The SYSREF± signal is a differential source synchronous input that

synchronizes the LMFC signals in both the transmitter and receiver

in a JESD204B Subclass 1 system to achieve deterministic latency.

The SYSREF± signal is a rising edge sensitive signal that is

sampled by the device clock rising edge. It is best practice that

the device clock and SYSREF± signals be generated by the

same source, such as the HMC7044 clock generator, so that the

phase alignment between the signals is fixed. When designing

for optimum deterministic latency operation, consider the timing

distribution skew of the SYSREF± signal in a multipoint link system

(multichip).

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