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AD9173 Datasheet(PDF) 94 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 94 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 94 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
5
DLL_CTRL1B
DLL control search mode. If the DAC frequency is
<4.5 GHz, set this bit to 0; otherwise, set this bit to 1.
0x1
R/W
[4:3]
DLL_CTRL1A
DLL control search direction. Set this control to 1 for
optimal performance.
0x2
R/W
[2:1]
RESERVED
Reserved.
0x0
R
0
DLL_ENABLE
DLL controller enable.
0x0
R/W
0
Disable DLL.
1
Enable DLL.
0x0C3
DLL_STATUS
[7:1]
RESERVED
Reserved.
0x0
R
0
DLL_LOCK
DLL lock indicator. This control reads back 1 if the
DLL locks.
0x0
R
0x0C7
DLL_READ
[7:1]
RESERVED
Reserved.
0x0
R
0
DLL_READ_EN
Enable DLL readback status. A transition of 0 to
1 updates the lock status bit readback in Register
0x0C3.
0x0
R/W
0x0CC
DLL_FINE_DELAY0
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
DLL_FINE_DELAY0
DLL delay control.
0x0
R/W
0x0CD
DLL_FINE_DELAY1
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
DLL_FINE_DELAY1
DLL delay control.
0x0
R/W
0x0DB
DLL_UPDATE
[7:1]
RESERVED
Reserved.
0x0
R
0
DLL_DELAY_
UPDATE
DLL update control. A transition from 0 to 1 updates
the DLL circuitry with the current register control
settings.
0x0
R/W
0x100
DIG_RESET
[7:1]
RESERVED
Reserved.
0x0
R
0
DIG_DATAPATH_
PD
Holds all digital logic (SERDES digital, digital clock
generation, and digital datapath) in reset until clock
tree is stable.
0x1
R/W
0
Normal operating mode.
1
Holds the digital logic in reset. Must be released (set
to 0) after clocks to the chip are stable (PLL and DLL
blocks are locked) to use the digital datapath.
0x110
JESD_MODE
7
MODE_NOT_IN_
TABLE
Programmed JESD204B mode and interpolation
mode combination is not valid. Select a different
combination.
0x0
R
6
COM_SYNC
Combine the signals in dual link case.
0x0
R/W
[5:0]
JESD_MODE
Sets the JESD204B mode configuration. See Table
13 for the JESD204B supported operating modes and
compatible interpolation rates. Bit 5 of this control
determines single link (set to 0) or dual link (set to 1).
Bits[4:0] set the desired JESD204B mode according
to Table 13.
0x20
R/W
0x111
INTRP_MODE
[7:4]
DP_INTERP_MODE
Sets main datapath interpolation rate. See Table
13 for the JESD204B supported operating modes
and compatible JESD204B modes and channel
interpolation rates.
0x8
R/W
0x1
1×.
0x2
2×.
0x4
4×.
0x6
6×.
0x8
8×.
0xC
12×.



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