AD9173 datasheet(42/144 Pages) AD

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Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

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Rev. C | 42 of 144

Link Delay Setup Example, With Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel.

The example shown in Figure 62 is demonstrated in the following

steps. Note that this example is in Subclass 1 to achieve determin-

istic latency, and the example uses the case for F = 2; therefore, the

number of PCLK cycles per multiframe = 16. Because PCBFixed

<< PCLK Period, PCBFixed is negligible in this example and not

included in the calculations.

1. Find the receiver delays using Table 6.

RxFixed = 13 PCLK cycles

RxVar = 2 PCLK cycles

2. Find the transmitter delays. The equivalent table in the example

JESD204B core (implemented on a GTH or GTX gigabit trans-

ceiver on a Virtex-6 field programmable gate array (FPGA))

states that the delay is 56 ± 2 byte clock cycles.

3. Because the PCLK rate = ByteRate/4 as described in the Clock

Relationships section, the transmitter delays in PCLK cycles are

calculated as follows:

TxFixed = 54/4 = 13.5 PCLK cycles

TxVar = 4/4 = 1 PCLK cycle

4. Calculate MinDelayLane as follows:

MinDelayLane = floorRxFixed+TxFixed+PCBFixed

= floor13+13.5+0

= floor26.5

MinDelayLane = 26

5. Calculate MaxDelayLane as follows:

MaxDelayLane = ceiling(RxFixed+RxVar+TxFixed+

TxVar+ PCBFixed)

= ceiling13+2+13.5+1+0

= ceiling29.5

MaxDelayLane = 30

6. Calculate LMFCVar as follows:

LMFCVar = MaxDelay+1 − MinDelay−1

= 30+1 − 26−1

= 31−25

LMFCVar = 6 PCLK cycles

7. Calculate LMFCDel as follows:

LMFCDel = MinDelay−1 % PCLKsperMF

= 26−1 %16

= 25%16

LMFCDel = 9 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the system.

Write LMFCVar to Register 0x306 for all devices in the system.

Link Delay Setup Example, Without Known

Delay

If the system delays are not known, the AD9173 can read back

the link latency between LMFCRX for each link (with the LMFCDel

setting subtracted out) and the SYSREF± aligned LMFC. This

information is then used to calculate LMFCVar and LMFCDel.

Figure 64 shows how DYN_LINK_LATENCY_0 (Register 0x302)

provides a readback showing the delay (in PCLK cycles) between

LMFCRX minus the LMFC_DELAY_x (fixed delay) setting set in the

SPI at that time and the transition from the ILAS to the first data

sample. By repeatedly power cycling and taking this measurement,

the minimum and maximum delays across power cycles can be

determined and used to calculate LMFCVar and LMFCDel.

In Figure 64, for Link A, Link B, and Link C, the system contain-

ing the AD9173 (including the transmitter) is power cycled and

configured 20 times. The AD9173 is configured as described in

the Sync Procedure section. Because the purpose of this exercise

is to determine LMFCDel and LMFCVar, the LMFCDel value is

programmed to 0 and the DYN_LINK_ LATENCY_0 value is read

from Register 0x302. The variation in the link latency over the 20

runs is shown in Figure 64, described as follows:

►

Link A gives readbacks of 6, 7, 0, and 1. Note that the set of

recorded delay values rolls over the edge of a multiframe at the

boundary of K/PCLK factor = 8. Add the number of PCLK cycles

per multiframe = 8 to the readback values of 0 and 1 because

they rolled over the edge of the multiframe. Delay values range

from 6 to 9.

►

Link B gives delay values from 5 to 7.

►

Link C gives delay values from 4 to 7.

The example shown in Figure 64 is demonstrated in the following

steps. Note that this example is in Subclass 1 to achieve determin-

istic latency, and the example uses the case for F = 1; therefore, the

number of PCLK cycles per multiframe = 8.

1. Calculate the minimum of all delay measurements across all

power cycles, links, and devices as follows:

MinDelay = min(all Delay values) = 4

2. Calculate the maximum of all delay measurements across all

power cycles, links, and devices as follows:

MaxDelay = max(all Delay values) = 9

3. Set LFMCVar to the maximum of 12 PCLK cycles. If latency is

required to be minimized for a given application, calculate the

total delay variation (with 2 PCLK cycles of guard band on each

end) across all power cycles, links, and devices as follows:

LMFCVar = MaxDelay+2 − MinDelay−2

= 9+2 − 4−2 =11−2=9 PCLK cycles

4. Calculate the minimum delay in PCLK cycles (with 2 PCLK cy-

cles of guard band) across all power cycles, links, and devices

as follows:

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