AD9173 datasheet(37/144 Pages) AD

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Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

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Rev. C | 37 of 144

Figure 56. Lane Alignment During ILAS

JESD204B Serial Link Establishment

A brief summary of the high speed serial link establishment process

for Subclass 1 is provided. See Section 5.3.3 of the JESD204B

specification document for complete details.

Step 1—Code Group Synchronization

Each receiver must locate /K/ (K28.5) characters in its input data

stream. After four consecutive /K/ characters are detected on all link

lanes, the receiver block deasserts the SYNCOUTx± signals to the

transmitter block at the receiver LMFC edge.

The transmitter captures the change in the SYNCOUTx± signals

and at a future transmitter LMFC rising edge, starts the ILAS.

Step 2—Initial Lane Alignment Sequence

The main purposes of this phase are to align all the lanes of the link

and to verify the parameters of the link.

Before the link is established, write each of the link parameters to

the receiver device to designate how data is sent to the receiver

block.

The ILAS consists of four or more multiframes. The last character

of each multiframe is a multiframe alignment character, /A/. The

first, third, and fourth multiframes are populated with predetermined

data values. Note that Section 8.2 of the JESD204B specifications

document describes the data ramp that is expected during the

ILAS. The deframer uses the final /A/ of each lane to align the

ends of the multiframes within the receiver. The second multiframe

contains an /R/ (K.28.0), /Q/ (K.28.4), and then data corresponding

to the link parameters. Additional multiframes can be added to the

ILAS if needed by the receiver. By default, the AD9173 uses four

multiframes in the ILAS (this can be changed in Register 0x478). If

using Subclass 1, exactly four multiframes must be used.

After the last /A/ character of the last ILAS, multiframe data begins

streaming. The receiver adjusts the position of the /A/ character

such that it aligns with the internal LMFC of the receiver at this

point.

Step 3—Data Streaming

In this phase, data is streamed from the transmitter block to the

receiver block.

Optionally, data can be scrambled. Scrambling does not start until

the first octet following the ILAS.

The receiver block processes and monitors the data it receives for

errors, including the following:

►

Bad running disparity (8-bit/10-bit error)

►

Not in table (8-bit/10-bit error)

►

Unexpected control character

►

Bad ILAS

►

Interlane skew error (through character replacement)

If any of these errors exist, they are reported back to the transmitter

in one of the following ways (see the JESD204B Error Monitoring

section for details):

►

SYNCOUTx± signal assertion: resynchronization (SYNCOUTx±

signals pulled low) is requested at each error for the last two

errors. For the first three errors, an optional resynchronization

request can be asserted when the error counter reaches a set

error threshold.

►

For the first three errors, each multiframe with an error in it

causes a small pulse on the respective SYNCOUTx± pins.

►

Errors can optionally trigger an interrupt request (IRQ) event,

which can be sent to the transmitter.

For more information about the various test modes for verifying the

link integrity, see the JESD204B Test Modes section.

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