AD9173 datasheet(26/144 Pages) AD

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Data Sheet

AD9173

THEORY OF OPERATION

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Rev. C | 26 of 144

The AD9173 is a 16-bit, dual RF DAC with a high speed JESD204B

SERDES interface, compliant with Subclass 0 and Subclass 1 oper-

ation. Figure 1 shows a functional block diagram of the AD9173.

Each DAC core has three individually bypassable channelizers

that support up to 1.54 GSPS of complex data rate input per

channel. Eight high speed serial lanes carry data at a maximum of

15.4 Gbps to the channel datapaths. The JESD204B interface sup-

ports both single-link and dual-link modes of operation, depending

on the selected mode configuration. Compared to either LVDS or

CMOS interfaces, the SERDES interface simplifies pin count, board

layout, and input clock requirements to the device.

The clock for the input data is derived from the DAC clock, or

device clock (required by the JESD204B specification). This device

clock can be sourced with a PLL reference clock used by the

on-chip PLL to generate a DAC clock, or a high fidelity, direct

external DAC sampling clock. The device can be configured to

operate in one-, two-, three-, four-, or eight-lane per link modes,

depending on the required input data rate.

The digital datapath of the AD9173 offers bypassable (1×) inter-

polation modes for both the channel datapaths and the main

datapaths. Additionally, depending on the selected mode, there

are also 2×, 3×, 4×, 6×, and 8× interpolation options for the channel

datapaths, and 2×, 4×, 6×, 8×, and 12× interpolation options for

the main datapaths. See Table 13 for a summary of the various

JESD204B modes available, as well as the respective interpolation

options.

For each of the channel digital datapaths (when not using 1×

interpolation for the channel), there are individually programmable

gain stages and NCO blocks available. The NCO blocks have a

48-bit modulus NCO option to enable digital frequency shifts of

signals with near infinite precision.

The NCO can operate alone in NCO only mode using a program-

mable dc value input via the SPI or with digital data from the

SERDES interface and digital datapath. At the end of the three

channelizer datapaths, a summation node combines the three

channel datapaths together at a maximum of 1.54 GSPS to then

pass along to each of the main DAC datapaths for further digital

feature options.

Each of the main DAC datapaths contain an optional power amplifi-

er (PA) protection block, a main datapath interpolation block, a main

NCO with an optional modulus feature, and a ramp-up/ramp-down

gain block that is fed by the PA protection block. Additionally, there

is an optional calibration tone feature, as well as four modulator

switch modes that are part of the main NCO block.

The AD9173 is capable of multichip synchronization that can both

synchronize multiple DACs and establish a constant and determin-

istic latency (latency locking) path for the DACs. The latency for

each of the DACs remains constant to within several DAC clock

cycles from link establishment to link establishment. An external

alignment signal (SYSREF±) makes the AD9173 JESD204B Sub-

class 1 compliant. Several modes of SYSREF± signal handling are

available for use in the system.

An SPI configures the various functional blocks and monitors their

statuses. The various functional blocks and the data interface must

be set up in a specific sequence for proper operation (see the

Start-Up Sequence section). Simple SPI initialization routines set

up the JESD204B link and are included in the evaluation board

software support.

This data sheet describes the various blocks of the AD9173 in

detail. Descriptions of the JESD204B interface, control parameters,

and various registers to set up and monitor the device are provided.

The recommended start-up routine reliably sets up the data link.

Table 13. JESD204B Supported Operating Modes and Interpolation Combinations

Application

JESD204B Operation Modes

Channel Datapath

Main DAC Datapath

Link Modes

JESD204B

Modes

Lanes per

Link

Channels

per DAC

Maximum

Channel Data

Rate (MSPS)1

Channel

Interpolations

Main Datapath

Interpolations

Maximum DAC Rate

(GSPS)2

Single-Channel, 375 MHz

(N = 16 Bits)

Single, dual 0

385

2×

4×, 6×

8×

6×, 8×

6.16

12.6

Dual-Channel, 375 MHz

(N = 16 Bits)

Single, dual 1

385

4×, 6×

6×, 8×

12.6

Triple-Channel, 375 MHz

(N = 16 Bits)

Single, dual 2

385

4×, 6×

6×, 8×

12.6

Single Channel, 500 MHz Single, dual 5

513

2×

6×

6.16

(N = 12 Bits, NP = 12 Bits)

3×

6×, 8×

12.6

Dual Channel, 500 MHz

(N = 12 Bits, NP = 12 Bits)

Single, dual 6

513

3×

6×, 8×

12.6

Single Channel, 750 MHz Single, dual 3

770

1×

8×

6.16

(N = 16 Bits)

2×, 3×

6×, 8×

12.6

Dual Channel, 750 MHz

Single, dual 4

770

2×, 3×

6×, 8×

12.6

(N = 16 Bits)

385

4×

8×

12.6

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