AD9173 datasheet(45/144 Pages) AD

45 / 144 page

Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

analog.com

Rev. C | 45 of 144

Configuration Parameters

The AD9173 modes refer to the link configuration parameters for

L, K, M, N, NP, S, and F. Table 30 provides the description and

addresses for these settings.

Table 30. Configuration Parameters

JESD204B

Setting

Description

Address

L − 1

Number of lanes minus 1.

Bits[4:0]

F − 1

Number of ((octets per frame) per lane)

minus 1.

Bits[7:0]

K − 1

Number of frames per multiframe minus

Bits[4:0]

M − 1

Number of converters minus 1.

Bits[7:0]

N − 1

Converter bit resolution minus 1.

Bits[4:0]

NP − 1

Bit packing per sample minus 1.

Bits[4:0]

S − 1

Number of ((samples per converter) per

frame) minus 1.

Bits[4:0]

High density format. Set to 1.

DID

Device ID. Match the device ID sent by

the transmitter.

Bits[7:0]

BID

Bank ID. Match the bank ID sent by the

transmitter.

Bits[7:0]

LID0

Lane ID for Lane 0. Match the Lane ID

sent by the transmitter on Logical Lane 0.

Bits[4:0]

JESDV

JESD204x version. Match the version

sent by the transmitter (0x0 = JESD204A,

0x1 = JESD204B).

Bits[7:5]

The AD9173 truncates the output of the main digital datapath to the

value of N bits for the selected mode, which is then sent to the DAC

core. It is possible to send the value of NP number of bits worth of

data with the lower NP − N LSBs padded as 0s, or to send the full

NP number of bits data across the SERDES lanes. In either case,

the lower NP − N LSBs are truncated prior to the DAC core.

Data Flow Through the JESD204B Receiver

The link configuration parameters determine how the serial bits on

the JESD204B receiver interface are deframed and passed on to

the DACs as data samples.

Deskewing and Enabling Logical Lanes

After proper configuration, the logical lanes are automatically de-

skewed. All logical lanes are enabled or not based on the number

of lanes for the mode setting chosen in Register 0x110, Bits[4:0].

The physical lanes are all powered up by default. To disable power

to physical lanes that are not being used, set Bit x in Register

0x201 to 1 to disable Physical Lane x, and keep it at 0 to enable

it. The logical lanes must be enabled and deskewed on a per link

basis using the LINK_PAGE control (Register 0x300, Bit 2). Set Bit

x in Register 0x46C to 1 to deskew Link Logical Lane x for the

selected link page.

JESD204B TEST MODES

PHY PRBS Testing

The JESD204B receiver on the AD9173 includes a PRBS pattern

checker on the back end of its physical layer. This functionality

enables bit error rate (BER) testing of each physical lane of the

JESD204B link. The PHY PRBS pattern checker does not require

that the JESD204B link be established. It can synchronize with a

PRBS7, PRBS15, or PRBS31 data pattern. PRBS pattern verifica-

tion can be performed on multiple lanes at once. The error counts

for failing lanes are reported for one JESD204B lane at a time. The

process for performing PRBS testing on the AD9173 is as follows:

1. Start sending a PRBS7, PRBS15, or PRBS31 pattern from the

JESD204B transmitter.

2. Select and write the appropriate PRBS pattern to Regis-

ter 0x316, Bits[3:2], as shown in Table 31.

3. Enable the PHY test for all lanes being tested by writing to

PHY_TEST_EN (Register 0x315). Each bit of Register 0x315

enables the PRBS test for the corresponding lane. For exam-

ple, writing a 1 to Bit 0 enables the PRBS test for Physical Lane

4. Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0 to 1

then back to 0.

5. Set PHY_PRBS_TEST_THRESHOLD_xBITS (Bits[23:0], Reg-

ister 0x319 to Register 0x317) as desired.

6. Write a 0 and then a 1 to PHY_TEST_START (Register 0x316,

Bit 1). The rising edge of PHY_TEST_START starts the test.

a. (Optional) In some cases, it may be necessary to repeat

Step 4 at this point. Toggle PHY_TEST_RESET (Register

0x316, Bit 0) from 0 to 1, then back to 0.

7. Wait 500 ms.

8. Stop the test by writing PHY_TEST_START (Register 0x316,

Bit 1) = 0.

9. Read the PRBS test results.

a. Each bit of PHY_PRBS_PASS (Register 0x31D) corre-

sponds to one SERDES lane (0 = fail, 1 = pass).

b. The number of PRBS errors seen on each failing lane can

be read by writing the lane number to check (0 to 7) in

PHY_SRC_ERR_CNT (Register 0x316, Bits[6:4]) and read-

ing the PHY_PRBS_ERR_CNT_xBITS (Register 0x31A to

all bits of Register 0x31A to Register 0x31C are high, the

maximum error count on the selected lane is exceeded.

AD9173 Datasheet(PDF) 45 Page - Analog Devices

AD9173 Datasheet(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL