AD9173 datasheet(35/144 Pages) AD

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Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

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Rev. C | 35 of 144

The processing clock is used for a quad-byte decoder.

Frame Rate = Byte Rate/F

where F is defined as octets per frame per lane.

PCLK Factor = Frame Rate/PCLK Rate = 4/F

where:

M is the JESD204B parameter for converters per link.

L is the JESD204B parameter for lanes per link.

F is the JESD204B parameter for octets per frame per lane.

NP is the JESD204B parameter for the total number of bits

per sample.

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES PLL uses integer N techniques to ach-

ieve clock synthesis. The entire SERDES PLL is integrated on chip,

including the VCO and the loop filter. The SERDES PLL is capable

of providing quadrature clocks to allow a wide range of data rates

(3 Gbps to 15 Gbps) with no gaps.

These clocks are the input to the CDR block that is described in the

Clock and Data Recovery section.

The reference clock to the SERDES PLL is always running at

a frequency, fREF, that is equal to 1/40 of the lane rate (PCLK

rate). For more information about the SERDES circuitry setup and

relevant register writes, see the Start-Up Sequence section. The

SERDES PLL block automatically tunes to the appropriate divider

range for the lane rate based on the SERDES mode being used.

It takes the DAC clock generated by either the DAC PLL, if in use,

or from the direct clock being sourced at the CLKIN± pins, divides

the DAC clock frequency by 4, and uses the JESD204B parameters

corresponding to the mode and interpolation values programmed in

for generating the PCLK frequency (lane rate ÷ 40), as shown in

Figure 51.

Confirm that the SERDES PLL is working by reading Regis-

ter 0x281. If Register 0x281, Bit 0 = 1, the SERDES PLL has

locked.

Clock and Data Recovery

The deserializer is equipped with a CDR circuit. Instead of recover-

ing the clock from the JESD204B serial lanes, the CDR recovers

the clocks from the SERDES PLL.

The CDR circuit synchronizes the phase used to sample the

data on each serial lane independently. This independent phase

adjustment per serial interface ensures accurate data sampling and

eases the implementation of multiple serial interfaces on a PCB.

Power-Down Unused PHYs

Note that any unused physical and enabled lanes consume extra

power unnecessarily. Each lane that is not being used (SERDINx±)

must be powered off by writing a 1 to the corresponding bit of

PHY_PD (Register 0x201).

Equalization

To compensate for signal integrity distortions for each PHY channel

due to PCB trace length and impedance, the AD9173 employs

an easy to use, low power equalizer on each JESD204B channel.

The AD9173 equalizers operating at the maximum lane rate of

15 Gbps can compensate for up to 16 dB of insertion loss. This

equalizer performance is shown in Figure 52 for 15 Gbps, near

the maximum baud rate for the AD9173. The channel must also

meet the insertion loss deviation requirement of the JESD204B

specification (less than 1.5 dB from 50 MHz to 0.75 times the baud

rate).

Figure 52. Insertion Loss Allowed

To ensure the AD9173 compensates for the amount of insertion

loss in the system, set the equalizer block appropriately. Table 22

shows the settings for the equalizer boost, equalizer gain, and

feedback controls, depending on the level of insertion loss in the

system. The equalizer boost setting is programmed for each PHY

lane (2-bit control for each) being used in Register 0x240 and Reg-

ister 0x241. Similarly, the equalizer gain settings are programmed

for each PHY lane (2-bit control for each) used in Register 0x242

and Register 0x243. The feedback control is programmed per PHY

lane (5-bit control for each, one control per register) in Register

0x244 to Register 0x24B.

Table 22. Equalizer Register Control Settings per PHY Control

Insertion Loss

≤11 dB

>11 dB

Equalizer Boost

0x02

0x03

Equalizer Gain

0x01

0x03

Feedback

0x1F

Figure 53 and Figure 54 are provided as points of reference

for hardware designers and show the insertion loss for various

lengths of well laid out stripline and microstrip transmission lines,

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