AD9173 datasheet(65/144 Pages) AD

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Data Sheet

AD9173

ANALOG INTERFACE CONSIDERATIONS

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Rev. C | 65 of 144

DAC On-Chip PLL

When using the on-chip PLL, the predivider setting is selected (via

internally to be within the range of 25 MHz to 770 MHz for the

phase frequency detector (PFD) circuitry block input.

The AD9173 DAC VCO operates over a frequency range of

8.74 GHz to 12.4 GHz. Enable the DAC PLL synthesizer by

setting Register 0x095, Bit 0 to 0. The DAC clock rate is user

configurable to be the VCO frequency (8.74 GHz to 12.4 GHz), the

VCO frequency divided by 2 (4.37 GHz to 6.2 GHz), or the VCO

frequency divided by 3 (2.92 GHz to 4.1 GHz) by setting Register

0x094, Bits[1:0]. See the Start-Up Sequence section for instructions

on how to program the PLL.

The AD9173 DAC PLL requires an external loop filter. The recom-

mended filter is a standard passive filter, as shown in Figure 88.

The user can customize the filter according to the PFD frequen-

cy, reference clock phase noise, and DAC output phase noise

requirements. For lowest jitter applications, use the highest possible

PFD frequency to minimize the contribution of in-band noise from

the PLL. However, when operating with a VCO frequency from

9.96 GHz to 10.87 GHz, set the PFD frequency to less than 225

MHz to ensure optimized stability over temperature.

Set the PLL filter bandwidth such that the in‑band noise of the

PLL intersects with the open-loop noise of the VCO, minimizing the

contribution of both to the overall noise.

The DAC PLL uses an integer type synthesizer to achieve the DAC

sampling clock. The relation between DAC clock and the reference

clock is as follows:

fDAC = (8 × N × fREF)/M/(Register 0x094, Bits[1:0] + 1)

where:

fDAC is the desired DAC clock rate.

N is the VCO feedback divider ratio, ranging from 2 to 50.

fREF is the reference clock.

M is the reference clock divider ratio; the valid values for reference

clock divider (predivider) are 1, 2, 3, or 4 by setting Register 0x793,

Bits[1:0].

The VCO automatic calibration is triggered by the falling edge of

lock detector bit (Register 0x7B5, Bit 0) is provided to indicate that

the DAC PLL achieved lock. If Register 0x7B5, Bit 0 = 1, the PLL

has locked.

Figure 88. DAC PLL and Clock Path Block Diagram

AD9173 Datasheet(PDF) 65 Page - Analog Devices

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