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AD9173 Datasheet(PDF) 92 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 92 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 92 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0
CAL_FINISH
Calibration complete flag. A readback of 1 indicates
the calibration completed. This control is paged by the
MAINDAC_PAGE bits in Register 0x008.
0x0
R
0x059
FSC0
[7:2]
RESERVED
Reserved.
0xA
R/W
[1:0]
FSC_CTRL[1:0]
Sets the full-scale current control. This control is
paged by the MAINDAC_PAGE bits in Register
0x008. Full-scale current = 16 mA + FSC_CTRL ×
(25/1024) (mA).
0x0
R/W
0x05A
FSC1
[7:0]
FSC_CTRL[9:2]
Sets the full-scale current control. This control is
paged by the MAINDAC_PAGE bits in Register
0x008. Full-scale current = 16 mA + FSC_CTRL ×
(25/1024) (mA).
0x28
R/W
0x061
CAL_DEBUG0
7
RESERVED
Reserved.
0x0
R/W
6
CAL_CTRL2
Calibration control. Set this bit to 1 for optimized
calibration setting.
0x1
R/W
5
CAL_CTRL3
Calibration control. Set this bit to 1 for optimized
calibration setting.
0x1
R/W
4
RESERVED
Reserved.
0x0
R/W
3
CAL_CTRL4
Calibration control. Set this bit to 1 for optimized
calibration setting.
0x0
R/W
[2:0]
RESERVED
Reserved.
0x0
R/W
0x081
CLK_CTRL
[7:2]
RESERVED
Reserved.
0x0
R/W
1
CAL_CLK_PD1
After the calibration is complete for DAC1 (Register
0x052, Bit 0 = 1), set this bit high to power down the
calibration clock.
0x0
R/W
0
CAL_CLK_PD0
After the calibration is complete for DAC0 (Register
0x052, Bit 0 = 1), set this bit high to power down the
calibration clock.
0x0
R/W
0x083
NVM_CTRL0
7
NVM_CTRL0A
NVM register control for the ring oscillator.
0x0
R/W
[6:2]
RESERVED
Reserved.
0x0
R
[1:0]
NVM_CTRL0B
NVM register control for the ring oscillator.
0x2
R/W
00
Divide by 8.
01
Divide by 16.
10
Divide by 32.
11
Divide by 64.
0x084
SYSREF_CTRL
7
RESERVED
Reserved.
0x0
R/W
6
SYSREF_
Sets the input mode type for the SYSREF± pins.
0x0
R/W
INPUTMODE
0
AC couple SYSREF±.
1
DC couple SYSREF±.
[5:1]
RESERVED
Reserved.
0x0
R/W
0
SYSREF_PD
Power down the SYSREF± receiver and
synchronization circuitry. If using Subclass 0, set this
bit to 1 because the SYSREF± pins are not used.
0x0
R/W
0
SYSREF± receiver is powered on.
1
SYSREF± receiver is powered down.
0x085
NVM_CTRL1
7
RESERVED
Reserved.
0x0
R
[6:4]
NVM_CTRL1A
NVM control.
0x1
R/W
[3:2]
RESERVED
Reserved.
0x0
R
1
NVM_CTRL1B
NVM control.
0x1
R/W
0
NVM_CTRL1C
NVM control.
0x1
R/W



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