AD9173 datasheet(40/144 Pages) AD

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Data Sheet

AD9173

JESD204B SERIAL DATA INTERFACE

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Rev. C | 40 of 144

synchronization.

3. If Subclass 1, configure the SYSREF± settings as follows:

a. Set Register 0x039 (SYSREF± jitter window). See Table 24

for settings.

b. Set Register 0x036 = SYSREF_COUNT; leave as 0 to

bypass.

4. Perform a one-shot sync.

a. Set Register 0x03A = 0x00. Clear one-shot mode if already

enabled.

b. Set Register 0x03A = 0x02. Enable one-shot sync mode.

5. If Subclass 1, send a SYSREF± edge. If pulse counting, multi-

ple SYSREF± edges are required. Sending SYSREF± edges

triggers the synchronization.

6. Read back the SYNC_ROTATION_DONE bit (Register 0x03A,

Bit 4) to confirm the rotation occurred.

Resynchronizing LMFC Signals

If desired, the sync procedure can be repeated to realign the

LMFC clock to the reference signal by repeating Step 2 to Step 6,

described in the Sync Procedure section. When the one‑shot sync

is triggered (writing Register 0x03A = 0x02), the SYNCOUTx±

signals deassert to drop the JESD204B links and reassert the links

after the rotation completes.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout. Data traversing from one clock domain to a different

clock domain can lead to ambiguous delays in the JESD204B link.

These ambiguities lead to nonrepeatable latencies across the link

from power cycle to power cycle with each new link establishment.

Section 6 of the JESD204B specification addresses the issue of

deterministic latency with mechanisms defined as Subclass 1 and

Subclass 2.

The AD9173 supports JESD204B Subclass 0 and Subclass 1 oper-

ation, but not Subclass 2. Write the subclass to Register 0x458,

Bits[7:5].

Subclass 0

This mode gives deterministic latency to within several PCLK cy-

cles. It does not require any signal on the SYSREF± pins, which

can be left disconnected.

Subclass 0 requires that all lanes arrive within the same LMFC

cycle and the dual DACs must be synchronized to each other.

Subclass 1

This mode gives deterministic latency and allows the link to be

synchronized to within a few DAC clock cycles. Across the full

operating range, for both supply and temperature, it is within ±2.5

DAC clock periods for a 6 GHz DAC clock rate or ±4 DAC clock

periods for a 12.6 GHz DAC clock rate. If both supply and tempera-

ture stability are maintained, the link can be synchronized to within

±1.5 DAC clock periods for a 6 GHz DAC clock rate or ±2.5 DAC

clock periods for a 12.6 GHz DAC clock rate. Achieving this latency

requires an external, low jitter SYSREF± signal that is accurately

phase aligned to the DAC clock.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic latency

in a JESD204B Subclass 1 system, as follows:

►

The SYSREF± signal distribution skew within the system must

be less than the desired uncertainty.

►

The total latency variation across all lanes, links, and devices

must be ≤12 PCLK periods, which includes both variable delays

and the variation in fixed delays from lane to lane, link to link,

and device to device in the system.

Figure 59. JESD204B Link Delay = Fixed Delay + Variable Delay

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