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AD9173 Datasheet(PDF) 87 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 87 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 87 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
2
EN_LANE_FIFO
Enable lane FIFO overflow/underflow interrupt.
0x0
R/W
1
EN_PRBSQ
Enable PRBS imaginary error interrupt.
0x0
R/W
0
EN_PRBSI
Enable PRBS real error interrupt.
0x0
R/W
0x021
IRQ_ENABLE0
[7:4]
RESERVED
Reserved.
0x0
R
3
EN_DAC0_CAL_
Enable DAC0 calibration complete interrupt.
0x0
R/W
DONE
[2:1]
RESERVED
Reserved.
0x0
R/W
0
EN_PAERR0
Enable PA protection error interrupt for DAC0.
0x0
R/W
0x022
IRQ_ENABLE1
[7:4]
RESERVED
Reserved.
0x0
R
3
EN_DAC1_CAL_
Enable DAC1 calibration complete interrupt.
0x0
R/W
DONE
[2:1]
RESERVED
Reserved.
0x0
R/W
0
EN_PAERR1
Enable PA protection error interrupt for DAC1.
0x0
R/W
0x023
IRQ_ENABLE2
[7:6]
RESERVED
Reserved.
0x0
R
5
EN_DLL_LOST
Enable DLL lock lost interrupt.
0x0
R/W
4
EN_DLL_LOCK
Enable DLL lock interrupt.
0x0
R/W
[3:2]
RESERVED
Reserved.
0x0
R/W
1
EN_PLL_LOST
Enable PLL lock lost interrupt.
0x0
R/W
0
EN_PLL_LOCK
Enable PLL lock interrupt.
0x0
R/W
0x024
IRQ_STATUS
[7:5]
RESERVED
Reserved.
0x0
R
4
IRQ_SYSREF_JITTER
SYSREF± jitter too large. If EN_SYSREF_JITTER
is low, IRQ_SYSREF_JITTER shows the
current status. If EN_SYSREF_JITTER is high,
IRQ_SYSREF_JITTER latches and pulls the IRQx pin
low (x = the MUX_SYSREF_JITTER setting). Writing
a 1 to IRQ_SYSREF_JITTER when latched clears the
bit.
0x0
R/W
3
IRQ_DATA_READY
JESD204x receiver data ready is low. If
EN_DATA_READY is low, IRQ_DATA_READY shows
the current status. If EN_DATA_
0x0
R/W
READY is high, IRQ_DATA_READY latches and pulls
the IRQx pin low (x = MUX_
DATA_READY setting). Writing a 1 to IRQ_
DATA_READY when latched clears the bit.
2
IRQ_LANE_FIFO
Lane FIFO overflow/underflow. If EN_
0x0
R/W
LANE_FIFO is low, IRQ_LANE_FIFO shows
the current status. If EN_LANE_FIFO is high,
IRQ_LANE_FIFO latches and pulls the IRQx pin
low (x = MUX_LANE_FIFO setting). Writing a 1 to
IRQ_LANE_FIFO when latched clears the bit.
1
IRQ_PRBSQ
DAC1 PRBS error. If EN_PRBSQ is low, IRQ_PRBSQ
shows the current status. If EN_PRBSQ is high,
IRQ_PRBSQ latches and pulls the IRQx pin low (x
= MUX_PRBSQ setting). Writing a 1 to IRQ_PRBSQ
when latched clears the bit.
0x0
R/W
0
IRQ_PRBSI
DAC0 PRBS error. If EN_PRBSI is low, IRQ_
0x0
R/W
PRBSI shows the current status. If EN_PRBSI is high,
IRQ_PRBSI latches and pulls the IRQx pin low (x
= MUX_PRBSI setting). Writing a 1 to IRQ_PRBSI
when latched clears the bit.
0x025
IRQ_STATUS0
[7:4]
RESERVED
Reserved.
0x0
R



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