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AD9173 Datasheet(PDF) 90 Page - Analog Devices |
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AD9173 Datasheet(HTML) 90 Page - Analog Devices |
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90 / 144 page  Data Sheet AD9173 REGISTER DETAILS analog.com Rev. C | 90 of 144 Table 60. Register Details Addr. Name Bits Bit Name Settings Description Reset Access 1 MUX_PLL_LOST If EN_PLL_LOST is set, this control chooses the IRQx pin on which the event is triggered. 0x0 R/W 0 Route IRQ trigger signal to the IRQ0 pin. 1 Route IRQ trigger signal to the IRQ1 pin. 0 MUX_PLL_LOCK If EN_PLL_LOCK is set, this control chooses the IRQx pin on which the event is triggered. 0x0 R/W 0 Route IRQ trigger signal to the IRQ0 pin. 1 Route IRQ trigger signal to the IRQ1 pin. 0x02C IRQ_STATUS_ALL [7:1] RESERVED Reserved. 0x0 R 0 IRQ_STATUS_ALL This bit is an OR of all the bits in Register 0x24 to Register 0x27. Writing a one to this bit clears any latched IRQx signals in Register 0x24 to Register 0x27. 0x0 R/W 0x036 SYSREF_COUNT [7:0] SYSREF_COUNT Number of rising SYSREF± edges to ignore before synchronization (pulse counting mode). 0x0 R/W 0x039 SYSREF_ERR_ 7 RESERVED Reserved. 0x0 R WINDOW [6:0] SYSREF_ERR_ WINDOW Amount of jitter allowed on the SYSREF± input. SYSREF± jitter variations larger than this trigger an interrupt. Units are in DAC clocks. 0x0 R/W 0x03A SYSREF_MODE [7:5] RESERVED Reserved. 0x0 R 4 SYNC_ROTATION_DO NE Synchronization logic rotation complete flag. 0x1 R [3:2] RESERVED Reserved. 0x0 R 1 SYSREF_MODE_ Enable one-shot synchronization rotation mode. 0x0 R/W ONESHOT 00 Monitor mode. Status/error flag for IRQ_SYSREF_JITTER is 1 if the SYSREF± edge is outside the error window (Register 0x039, Bits[6:0]). 01 Perform a single synchronization on the next SYSREF±, then switch to monitor mode. 0 RESERVED Reserved. 0x0 R/W 0x03B ROTATION_MODE 7 SYNCLOGIC_EN This bit must always be set to 1 (default) for both Subclass 0 and Subclass 1 operations. 0x1 R/W 6 RESERVED Reserved. For proper operation, write this bit to a 1. 0x0 R/W 5 PERIODIC_RST_EN Synchronization required setting. Always set this bit to 1 for both Subclass 0 and Subclass 1 operation. 0x1 R/W 4 NCORST_AFTER_ ROT_EN Set this bit to 1 to reset all NCOs after digital reset or synchronization rotation. Either this control or the START_NCO_SYNC bit (Register 0x1E7, Bit 0) can be used to reset all the NCOs (main and channel datapaths). 0x1 R/W [3:2] RESERVED Reserved. 0x0 R [1:0] ROTATION_MODE Selects the circuitry to be reset when a synchronization rotation occurs. Certain bits being set to 1 determine the actions taken when a synchronization rotation is performed. Bit 0 corresponds to a SERDES clock reset and realignment. Bit 1 corresponds to a datapath soft off/on gain, which must only be used if PA protection is in use. If PA protection is not used, set Bit 1 to 0. 0x0 R/W 0 No action, with either the SERDES clocks or the datapath, occurs when a synchro-nization rotation occurs. |
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