AD9173 datasheet(5/144 Pages) AD

5 / 144 page

Data Sheet

AD9173

SPECIFICATIONS

analog.com

Rev. C | 5 of 144

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DAC UPDATE RATE

Minimum

2.91

GSPS

Maximum1

16-bit resolution, with interpolation

12.6

GSPS

11-bit resolution, with interpolation

12.6

GSPS

11-bit resolution, no interpolation

3.4

GSPS

Adjusted2

16-bit resolution, with interpolation3

1.23

GSPS

11-bit resolution, with interpolation

1.54

GSPS

11-bit resolution, no interpolation4

3.4

GSPS

DAC PHASE-LOCKED LOOP (PLL) VOLTAGE CONTROLLED OSCILLATOR (VCO)

FREQUENCY RANGES

VCO Output Divide by 1

8.74

12.42

GSPS

VCO Output Divide by 2

4.37

6.21

GSPS

VCO Output Divide by 3

2.91

4.14

GSPS

PHASE FREQUENCY DETECT INPUT FREQUENCY RANGES

9.96 GHz ≤ VCO Frequency ≤ 10.87 GHz

225

MHz

VCO Frequency < 9.96 GHz or VCO Frequency > 10.87 GHz

770

MHz

DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN−) FREQUENCY RANGES

PLL Off

2.91

12.6

GHz

PLL On

M divider set to divide by 1

770

MHz

M divider set to divide by 2

1540

MHz

M divider set to divide by 3

2310

MHz

M divider set to divide by 4

100

3080

MHz

1 The maximum DAC update rate varies depending on the selected JESD204B mode and the lane rate for the given configuration used. The maximum DAC rate according

to lane rate and voltage supply levels is listed in Table 3.

2 The adjusted DAC update rate is calculated as fDAC, divided by the minimum required interpolation factor for a given mode or the maximum channel data rate for a given

mode. Different modes have different maximum DAC update rates, minimum interpolation factors, and maximum channel data rates, as shown in Table 13.

3 The adjusted DAC update rate of 1.23 GSPS is the maximum for any 16-bit resolution mode of operation. See Table 13 for more details.

4 The adjusted DAC update rate of 3.4 GSPS is the maximum for any 11-bit resolution mode of operation. See Table 13 for more details.

MAXIMUM DAC SAMPLING RATE SPECIFICATIONS

AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise noted.

For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

MAXIMUM DAC UPDATE RATE

SVDD1.0 = 1.0 V ± 5%

Lane rate > 11 Gbps

11.67

GSPS

Lane rate ≤ 11 Gbps

12.37

GSPS

SVDD1.0 = 1.0 V ± 2.5%

Lane rate > 11 Gbps

11.79

GSPS

Lane rate ≤ 11 Gbps1

12.6

GSPS

1 If using the on-chip PLL, the maximum DAC speed is limited to the maximum PLL speed of 12.42 GSPS, as listed in Table 2.

AD9173 Datasheet(PDF) 5 Page - Analog Devices

AD9173 Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL