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AD9173 Datasheet(PDF) 32 Page - Analog Devices |
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AD9173 Datasheet(HTML) 32 Page - Analog Devices |
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32 / 144 page  Data Sheet AD9173 JESD204B SERIAL DATA INTERFACE analog.com Rev. C | 32 of 144 Table 18. Data Structure per Lane for F = 2 JESD204B Operating Modes1 JESD204B Mode and Parameters Link Logical Lane Frame 0 Frame 1 Octet 0 Octet 1 Octet 0 Octet 2 Mode 3 (L = 2, M = 2, S = 1, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] Lane 1 M1S0[15:8] M1S0[7:0] M1S1[15:8] M1S1[7:0] Mode 4 (L = 4, M = 4, S = 1, NP = 16, N = 16) Lane 0 M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] Lane 1 M1S0[15:8] M1S0[7:0] M1S1[15:8] M1S1[7:0] Lane 2 M2S0[15:8] M2S0[7:0] M2S1[15:8] M2S1[7:0] Lane 3 M3S0[15:8] M3S0[7:0] M3S1[15:8] M3S1[7:0] Mode 9 (L = 4, M = 2, S = 2, NP = 16, N = 16), Mode 14 (L = 4, M = 4, S = 2, NP = 16, N = 112) Lane 0 M0S0[15:8] M0S0[7:0] M0S2[15:8] M0S2[7:0] Lane 1 M0S1[15:8] M0S1[7:0] M0S3[15:8] M0S3[7:0] Lane 2 M1S0[15:8] M1S0[7:0] M1S2[15:8] M1S2[7:0] Lane 3 M1S1[15:8] M1S1[7:0] M1S3[15:8] M1S3[7:0] Mode 16 (L = 8, M = 2, S = 4, NP = 16, N = 112) Lane 0 M0S0[15:8] M0S0[7:0] M0S4[15:8] M0S4[7:0] Lane 1 M0S1[15:8] M0S1[7:0] M0S5[15:8] M0S5[7:0] Lane 2 M0S2[15:8] M0S2[7:0] M0S6[15:8] M0S6[7:0] Lane 3 M0S3[15:8] M0S3[7:0] M0S7[15:8] M0S7[7:0] Lane 4 M1S0[15:8] M1S0[7:0] M1S4[15:8] M1S4[7:0] Lane 5 M1S1[15:8] M1S1[7:0] M1S5[15:8] M1S5[7:0] Lane 6 M1S2[15:8] M1S2[7:0] M1S6[15:8] M1S6[7:0] Lane 7 M1S3[15:8] M1S3[7:0] M1S7[15:8] M1S7[7:0] 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. 2 Generate 11-bit resolution data and set Bits[4:0] to 0 for the full 16-bit data packing (NP). Table 19. Data Structure per Lane for F = 3 JESD204B Operating Modes1 JESD204B Mode and Parameters Link Logical Lane Frame 0 Octet 0 Octet 1 Octet 2 Nibble 0 Nibble1 Nibble 0 Nibble1 Nibble 0 Nibble1 Mode 5 (L = 1, M = 2, S = 1, NP = 12, N = 12) Lane 0 M0S0[11:8] M0S0[7:4] M0S0[3:0] M1S0[11:8] M1S0[7:4] M1S0[3:0] Mode 6 (L = 2, M = 4, S = 1, NP = 12, N = 12) Lane 0 M0S0[11:8] M0S0[7:4] M0S0[3:0] M1S0[11:8] M1S0[7:4] M1S0[3:0] Lane 1 M2S0[11:8] M2S0[7:4] M2S0[3:0] M3S0[11:8] M3S0[7:4] M3S0[3:0] Mode 17 (L = 8, M = 2, S = 8, NP = 12, N = 112) Lane 0 M0S0[11:8] M0S0[7:4] M0S0[3:0] M0S1[11:8] M0S1[7:4] M0S1[3:0] Lane 1 M0S2[11:8] M0S2[7:4] M0S2[3:0] M0S3[11:8] M0S3[7:4] M0S3[3:0] Lane 2 M0S4[11:8] M0S4[7:4] M0S4[3:0] M0S5[11:8] M0S5[7:4] M0S5[3:0] Lane 3 M0S6[11:8] M0S6[7:4] M0S6[3:0] M0S7[11:8] M0S7[7:4] M0S7[3:0] Lane 4 M1S0[11:8] M1S0[7:4] M1S0[3:0] M1S1[11:8] M1S1[7:4] M1S1[3:0] Lane 5 M1S2[11:8] M1S2[7:4] M1S2[3:0] M1S3[11:8] M1S3[7:4] M1S3[3:0] Lane 6 M1S4[11:8] M1S4[7:4] M1S4[3:0] M1S5[11:8] M1S5[7:4] M1S5[3:0] Lane 7 M1S6[11:8] M1S6[7:4] M1S6[3:0] M1S7[11:8] M1S7[7:4] M1S7[3:0] 1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. 2 Generate 11-bit resolution data and set Bit 0 to 0 for the full 12-bit data packing (NP). |
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