AD9173 datasheet(57/144 Pages) AD

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Data Sheet

AD9173

DIGITAL DATAPATH

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Rev. C | 57 of 144

Table 46. Main Datapath NCO FTW Registers

Address

Value

Description

0x114

DDSM_FTW[7:0]

8 LSBs of FTW

0x115

DDSM_FTW[15:8]

Next 8 bits of FTW

0x116

DDSM_FTW[23:16]

Next 8 bits of FTW

0x117

DDSM_FTW[31:24]

Next 8 bits of FTW

0x118

DDSM_FTW[39:32]

Next 8 bits of FTW

0x119

DDSM_FTW[47:40]

8 MSBs of FTW

Unlike other registers, the FTW registers are not updated immedi-

ately upon writing. Instead, the FTW registers update on the rising

edge of DDSM_FTW_LOAD_REQ (Register 0x113, Bit 0). After an

update request, DDSM_FTW_LOAD_ACK (Register 0x113, Bit 1)

must be high to acknowledge that the FTW updated.

The DDSM_SEL_SIDEBAND bit (Register 0x112, Bit 1 = 0b1) is a

convenience bit that can be set to use the lower sideband modula-

tion result, which is equivalent to flipping the sign of the FTW.

Figure 76. NCO Modulator Block Diagram

Main Datapath Modulus NCO Mode (Direct

Digital Synthesis (DDS))

Each of the main datapath 48-bit NCOs can also be used in a

dual modulus mode to create fractional frequencies beyond the

48-bit accuracy. The modulus mode is enabled by programming the

DDSM_MODULUS_EN bit in the DDSM_DATAPATH_CFG register

to 1 (Register 0x112, Bit 2 = 0b1).

The frequency ratio for the programmable modulus DDS is very

similar to that of the typical accumulator based DDS. The only

difference is that N is not required to be a power of two for the

programmable modulus, but can be an arbitrary integer. In practice,

hardware constraints place limits on the range of values for N. As a

result, the modulus extends the use of the NCO to applications that

require exact rational frequency synthesis. The underlying function

of the programmable modulus technique is to alter the accumulator

modulus.

Implementation of the programmable modulus function within the

AD9173 is such that the fraction, M/N, is expressible by the

following equation. Note that the form of the equation implies a

compound frequency tuning word with X representing the integer

part and A/B representing the fractional part.

fCARRIER

fDAC

=MN=X+AB248

where:

X is programmed in Register 0x114 to Register 0x119.

A is programmed in Register 0x12A to Register 0x12F.

B is programmed in Register 0x124 to Register 0x129.

Programmable Modulus Example

Consider the case in which fDAC = 12 GHz and the desired value of

fCARRIER is 1.2 GHz. This scenario synthesizes an output frequen-

cy that is not a power of two submultiple of the sample rate,

namely fCARRIER = (1/10) fNCO, which is not possible with a typical

accumulator based DDS. The frequency ratio, fCARRIER/fDAC, leads

directly to M and N, which are determined by reducing the fraction

(1,200,000,000/12,000,000,000) to its lowest terms, that is,

M/N = 1,200,000,000/12,000,000,000 = 1/10

Therefore, M = 1 and N = 10.

After calculation, X = 28,147,497,671,065, A = 3, and B = 5.

Programming these values into the registers for X, A, and B (X

is programmed in Register 0x114 to Register 0x119 for DDSM_

FTWx, B is programmed in Register 0x124 to Register 0x129 for

DDSM_ACC_MODULUSx, and A is programmed in Register 0x12A

to Register 0x12F for DDSM_ACC_DELTAx) causes the NCO to

produce an output frequency of exactly 1.2 GHz given a 12 GHz

sampling clock. For more details, refer to the AN-953 Application

Note.

NCO Reset

Resetting the NCO can be useful when determining the start time

and phase of the NCO. The NCO can be reset by several different

methods, including via an SPI write or by the SYSREF± signal.

Calibration NCO

There is an additional 32-bit calibration NCO option as part of the

main DAC NCO block, shown in Figure 68. Register 0x1E6, Bit 0

controls whether the 32-bit calibration NCO is in use in the main

datapath, or if the normal 48-bit main NCO is used. First, enable

the calibration NCO accumulator by setting Register 0x1E6, Bit 2

= 1. Then, program the calibration NCO FTW in Register 0x1E2

to Register 0x1E5 and update the FTW to take effect by toggling

used instead of the main NCO by setting Register 0x1E6, Bit 0 =

1 If using the calibration NCO along with the internal dc amplitude

level, enable the dc amplitude injection feature by setting Register

0x1E6, Bit 1 = 1.

Modulator Switch

The final DAC NCO block has an added functionality of a modulator

switch that allows the user to select the desired outputs of the NCO

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