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AD9173 Datasheet(PDF) 99 Page - Analog Devices |
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AD9173 Datasheet(HTML) 99 Page - Analog Devices |
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99 / 144 page  Data Sheet AD9173 REGISTER DETAILS analog.com Rev. C | 99 of 144 Table 60. Register Details Addr. Name Bits Bit Name Settings Description Reset Access 0x12D DDSM_ACC_DELTA3 [7:0] DDSM_ACC_ DELTA[31:24] Sets DDSM_ACC_DELTA. If DDSM_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/ DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x12E DDSM_ACC_DELTA4 [7:0] DDSM_ACC_ DELTA[39:32] Sets DDSM_ACC_DELTA. If DDSM_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/ DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x12F DDSM_ACC_DELTA5 [7:0] DDSM_ACC_ DELTA[47:40] Sets DDSM_ACC_DELTA. If DDSM_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/ DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x130 DDSC_DATAPATH_ 7 RESERVED Reserved. 0x0 R CFG 6 DDSC_NCO_EN Channel datapath modulation enable. If the JESD204B mode chosen is a complex mode (channel interpolation >1×), this bit must be set to 1 for each channel datapath being used. If no modulation is desired, set the FTW to 0. This control is paged by the CHANNEL_PAGE bits in Register 0x008. 0x0 R/W 0 Disable channel NCO. 1 Enable channel NCO. [5:3] RESERVED Reserved. 0x0 R/W 2 DDSC_MODULUS_EN Enable channel modulus DDS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. 0x0 R/W 0 Disable modulus DDS. 1 Enable modulus DDS. 1 DDSC_SEL_ SIDEBAND Selects upper or lower sideband from modulation result. This control is paged by the CHANNEL_PAGE bits in Register 0x008. 0x0 R/W 0 Use upper sideband. 1 Use lower sideband = spectral flip. 0 DDSC_EN_DC_ INPUT Enable test tone generation by sending dc to input level to channel DDS. Set the amplitude in the DC_TEST_INPUT_AMPLITUDE control (Register 0x148 and Register 0x149). This control is paged by the CHANNEL_PAGE bits in Register 0x008. 0x0 R/W 0 Disable test tone generation. 1 Enable test tone generation. 0x131 DDSC_FTW_UPDATE [7:3] RESERVED Reserved. 0x0 R 2 DDSC_FTW_ LOAD_SYSREF Use next rising edge of SYSREF± to trigger FTW load and reset. This control is paged by the CHANNEL_PAGE bits in Register 0x008. 0x0 R/W 1 DDSC_FTW_ LOAD_ACK Frequency tuning word update acknow-ledge bit. This bit reads back 1 if the FTW and phase offset word 0x0 R |
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