AD9173 datasheet(64/144 Pages) AD

64 / 144 page

Data Sheet

AD9173

ANALOG INTERFACE CONSIDERATIONS

analog.com

Rev. C | 64 of 144

DAC INPUT CLOCK CONFIGURATIONS

The AD9173 DAC sample clock or device clock (DACCLK) can be

sourced directly through CLKIN± (Pin H12 and Pin J12) or by using

the on-chip, integrated, integer PLL VCO with the same CLKIN± dif-

ferential input serving as the reference. Clock multiplying employs

the on-chip DAC PLL that accepts a reference clock operating at a

submultiple of the desired DACCLK rate. The PLL then multiplies

the reference clock up to the desired DACCLK frequency, which

generates all the clocks within the AD9173, as shown in Figure 88.

The AD9173 contains a low jitter, differential clock receiver that is

capable of interfacing directly to a differential or single-ended clock

source. Because the input is self biased with a nominal impedance

of 100 Ω, it is recommended that the clock source be ac-coupled

to the CLKIN± input pins. Improved phase noise performance can

be achieved with a higher clock input level. The quality of the

clock source, as well as its interface to the AD9173 clock input,

directly impacts ac performance. Select the phase noise and spur

characteristics of the clock source to meet the target application

requirements. The typical phase noise performance when directly

clocking the AD9173 with the input clock duty cycle correction on

(enabled by default) is shown in Figure 87 compared to the on-chip

PLL phase noise.

Figure 86. Clock Receiver Input Simplified Equivalent Circuit

Figure 87. Phase Noise vs. Frequency Offset; Direct Clock and PLL Phase Noise, 12 GHz DAC Sample Rate, 1.65 GHz Output Frequency

AD9173 Datasheet(PDF) 64 Page - Analog Devices