HC05 datasheet(145/232 Pages) MOTOROLA

145 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

10-11

RESETS AND INTERRUPTS

Note:

If the external interrupt function is disabled by the INTE bit and an external interrupt is

sensed by the edge detector circuitry, then the interrupt request is latched and the

interrupt stays pending until the INTE bit is set. The internal latch of the external

interrupt is cleared in the ﬁrst part of the service routine (except for the low level

interrupt which is not latched); therefore, only one external interrupt pulse can be

latched during tILIL and serviced as soon as the I-bit is cleared.

10.2.3.2

External interrupts

IRQ interrupt

If the interrupt mask in the condition code register has been cleared and the interrupt enable bit

(INTE) is set and the signal on the external interrupt pin (IRQ) satisﬁes the condition selected by

the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and

INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is

recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks

further interrupts until the present one is serviced. The external interrupt service routine address

is speciﬁed by the content of memory locations $3FFA and $3FFB.

Wired-OR interrupt (WOI)

An external WOI capability is provided on all port B I/O pins when they are programmed as inputs,

and on the NWOI pin. A WOI is activated only if WOIE in the EEPROM control register is set and

if wired-OR interrupts have been chosen as an option on the device (see Section 1.2). If wired-OR

interrupts are enabled on a given input pin (NWOI pin or port B pins; refer to Section 2.3.19 and

Section 4.2), an external interrupt is requested when this pin is pulled high. The request is serviced

by the interrupt routine whose start address is contained in memory locations $3FFA and $3FFB.

External and power-on reset clear the WOIE bit. A WOI interrupt will cause the MCU to exit STOP

mode.

The interrupt enable bit (INTE) in the miscellaneous register enables both wired-OR interrupts and

the IRQ interrupt. IRQ and WOI are internally OR-ed before interrupt sensitivity selection (see

Section 10.2.3.1).

10.2.3.3

MCAN interrupt (CIRQ)

Several sources can trigger a CIRQ. The MCAN interrupt register at $0023 is used to identify the

source. Each CIRQ source can be individually enabled (except the wake-up interrupt, which is

always enabled) by different bits of the MCAN control register at $0020.

The CIRQ sources are (also see Section 5.3.4):

Receive IRQ: this signals successful reception of a complete message.

Transmit IRQ: this signals successful transmission of a complete message.

143

HC05 Datasheet(PDF) 145 Page - Motorola, Inc

HC05 Datasheet(HTML) 145 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL