HC05 datasheet(143/232 Pages) MOTOROLA

143 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

10-9

RESETS AND INTERRUPTS

10.2.1

Interrupt priorities

Each potential interrupt source is assigned a priority level, which means that if more than one

interrupt is pending at the same time, the processor will service the one with the highest priority

ﬁrst. For example, if both an external interrupt and a timer interrupt are pending after an instruction

execution, the external interrupt is serviced ﬁrst.

Table 10-2 shows the relative priority of all the possible interrupt sources. Figure 10-4 shows the

interrupt processing ﬂow.

10.2.2

Nonmaskable software interrupt (SWI)

The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is

executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI

is executed after interrupts that were pending when the SWI was fetched, but before interrupts

generated after the SWI was fetched. The SWI interrupt service routine address is speciﬁed by the

contents of memory locations $3FFC and $3FFD.

10.2.3

Maskable hardware interrupts

If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are

masked. Clearing the I-bit allows interrupt processing to occur.

Note:

The internal interrupt latch is cleared in the ﬁrst part of the interrupt service routine;

therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit

is cleared.

Table 10-2 Interrupt priorities

Source

Flags

Vector address Priority

Reset

—

$3FFE, $3FFF

highest

Software interrupt (SWI)

—

$3FFC, $3FFD

External interrupt (IRQ) or WOI

—

$3FFA, $3FFB

Timer input captures

TSR

ICF1, ICF2

$3FF8, $3FF9

Timer output compares

TSR

OCF1, OCF2

$3FF6, $3FF7

Timer overﬂow

TSR

TOF

$3FF4, $3FF5

Serial communications

interface (SCI)

SCSR

TDRE, TC,

OR, RDRF,

IDLE

$3FF2, $3FF3

MCAN

CINT

WIF,OIF,EIF,

TIF, RIF

$3FF0, $3FF1

lowest

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