HC05 datasheet(140/232 Pages) MOTOROLA

140 / 232 page

MOTOROLA

10-6

MC68HC05X16

Rev. 1

RESETS AND INTERRUPTS

Table 10-1 Effect of RESET, POR, STOP and WAIT

Function/effect

RESET

POR

WAIT

STOP

Timer prescaler cleared

–

Timer counter set to $FFFC

–

All timer enable bits cleared (disable)

–

Data direction registers cleared (inputs)

–

Stack pointer set to $00FF

–

Internal address bus forced to restart

–

Vector $3FFE, $3FFF

–

Interrupt mask bit (I-bit CCR) set

–

Interrupt mask bit (I-bit CCR) cleared

–

Interrupt enable bit (INTE) set

–

POR bit in miscellaneous register set

–

STOP latch reset

–

IRQ latch reset

–

WAIT latch reset

–

SCI disabled

–

SCI status bits cleared (except TDRE

and TC)

–

SCI interrupt enable bits cleared

–

SCI status bits TDRE and TC set

–

Oscillator disabled for 4064 cycles

–

Timer clock cleared

–

SCI clock cleared

–

A/D disabled

–

SM bit in the miscellaneous register

cleared

x–x

Watchdog counter reset

WDOG bit in the miscellaneous register

reset

x–x

EEPROM control bits set or cleared (as

per Section 3.5.1)

x–x

x = Described action takes place

– = Described action does not take

place

138

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