HC05 datasheet(136/232 Pages) MOTOROLA

136 / 232 page

MOTOROLA

10-2

MC68HC05X16

Rev. 1

RESETS AND INTERRUPTS

10.1.1

Power-on reset

A power-on reset occurs when a positive transition is detected on VDD. The power-on reset

function is strictly for power turn-on conditions and should not be used to detect drops in the power

supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the

oscillator becomes active. If the external RESET pin is low at the end of this delay then the

processor remains in the reset state until RESET goes high. The user must ensure that the voltage

on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.

If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached

the speciﬁed minimum operating voltage. This may be accomplished by connecting an external RC

circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be great

enough to allow the oscillator circuit to stabilize.

During power-on reset, the RESET pin is driven low during a tPORL delay start-up sequence. tPORL is

deﬁned by a user speciﬁed mask option to be either 16 cycles or 4064 cycles (see Section 1.2).

A software distinction between a power-on reset and an external reset can be made using the POR

bit in the miscellaneous register (see Section 10.1.2).

10.1.2

Miscellaneous register

POR — Power-on reset bit

This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the

user to make a software distinction between a power-on and an external reset. This bit cannot be

set by software and is cleared by writing it to zero.

1 (set)

–

A power-on reset has occurred.

0 (clear) –

No power-on reset has occurred.

Note:

The bits shown shaded in the above representation are explained individually in the

relevant sections of this manual. The complete register plus an explanation of each bit

can be found in Section 3.8.

(1) The POR bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled,

0=watchdog disabled.

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Miscellaneous

$000C POR(1) INTP INTN INTE

SFA

SFB

SM WDOG(2) u001 000u

134

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