HC05 datasheet(134/232 Pages) MOTOROLA

134 / 232 page

MOTOROLA

9-6

MC68HC05X16

Rev. 1

ANALOG TO DIGITAL CONVERTER

9.4

A/D converter during WAIT mode

The A/D converter is not affected by WAIT mode and continues normal operation.

In order to reduce power consumption the A/D converter can be disconnected, under software

control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before

entering WAIT mode.

9.5

Port D analog input

The external analog voltage value to be processed by the A/D converter is sampled on an internal

capacitor through a resistive path, provided by input-selection switches and a sampling aperture

time switch, as shown in Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling,

the analog value is stored on the capacitor and held until the end of conversion. During this hold

time, the analog input is disconnected from the internal A/D system and the external voltage

source sees a high impedance input.

The equivalent analog input during sampling is an RC low-pass ﬁlter with a minimum resistance

of 50 k

Ω and a capacitance of at least 10pF. It should be noted that these are typical values

measured at room temperature.

Figure 9-2 Electrical model of an A/D input pin

Analog

input

Input protection device

VRL

< 2pF

+ ~20V

- ~0.7V

400 nA

junction

leakage

≥50kΩ

≥10pF

DAC

capacitance

Note:

The analog switch is closed during the 12 cycle sample

time only.

132

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