HC05 datasheet(130/232 Pages) MOTOROLA

130 / 232 page

MOTOROLA

9-2

MC68HC05X16

Rev. 1

ANALOG TO DIGITAL CONVERTER

The A/D reference input (AN0–AN7) is applied to a precision internal D/A converter. Control logic

drives this D/A converter and the analog output is successively compared with the analog input

sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.

The result of each successive comparison is stored in the SAR and, when the conversion is

complete, the contents of the SAR are transferred to the read-only result data register ($08), and

the conversion complete ﬂag, COCO, is set in the A/D status/control register ($09).

Warning: Any write to the A/D status/control register will abort the current conversion, reset the

conversion complete ﬂag and start a new conversion on the selected channel.

At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled.

Figure 9-1 A/D converter block diagram

AN0

VRH

(VRH+VRL)/2

VRL

A/D result register (ADDATA) $08

8-bit capacitive DAC

with sample and hold

VRH

VRL

Result

A/D status/control register (ADSTAT)$09

COCO

ADRC

ADON

CH3

CH2

CH1

CH0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Successive approximation

128

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