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HC05 Datasheet(PDF) 128 Page - Motorola, Inc |
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HC05 Datasheet(HTML) 128 Page - Motorola, Inc |
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128 / 232 page  MOTOROLA 8-4 MC68HC05X16 Rev. 1 PULSE LENGTH D/A CONVERTERS 8 8.2 PLM clock selection The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no effect on the D/A converters’ 8-bit resolution (see Figure 8-3). 8.3 PLM during STOP mode On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by power-on or external reset the registers values are forced to $00. 8.4 PLM during WAIT mode The PLM system is not affected by WAIT mode and continues normal operation. Figure 8-3 PLM clock selection fOSC ÷2 ÷32 SM bit = 0 SM bit = 1 ÷4 x4096 x256 SF bit = 1 SF bit = 0 Timer clock PLM clock Bus frequency (fOP) 126 |
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