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HC05 Datasheet(PDF) 101 Page - Motorola, Inc |
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HC05 Datasheet(HTML) 101 Page - Motorola, Inc |
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101 / 232 page  MC68HC05X16 Rev. 1 MOTOROLA 6-13 PROGRAMMABLE TIMER 6 Figure 6-2 Timer state timing diagram for reset Figure 6-3 Timer state timing diagram for input capture Internal processor clock Internal reset 16-bit counter External reset or end of POR Internal timer clocks $FFFC $FFFD $FFFE $FFFF Note: The counter and timer control registers are the only ones affected by power-on or external reset. T00 T01 T11 T10 Internal processor clock 16-bit counter $F123 $F124 $F125 $F126 Internal timer clocks T00 T01 T11 T10 Internal capture latch $F124 $???? Input capture register Input capture flag Input edge Note: If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then the input capture flag will be set during the next T11 state. 99 |
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