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HC05 Datasheet(PDF) 105 Page - Motorola, Inc

Part # HC05
Description  High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
PDF  232 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

HC05 Datasheet(HTML) 105 Page - Motorola, Inc

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MC68HC05X16
Rev. 1
MOTOROLA
7-3
SERIAL COMMUNICATIONS INTERFACE
7
7.2
SCI receiver features
•
Receiver wake-up function (idle line or address bit)
•
Idle line detection
•
Framing error detection
•
Noise detection
•
Overrun detection
•
Receiver data register full flag
7.3
SCI transmitter features
•
Transmit data register empty flag
•
Transmit complete flag
•
Send break
7.4
Functional description
A block diagram of the SCI is shown in Figure 7-1. Option bits in serial control register1 (SCCR1)
select the ‘wake-up’ method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides
control bits that individually enable the transmitter and receiver, enable system interrupts and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud
rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and
receiver (see Section 7.11.5).
Data transmission is initiated by writing to the serial communications data register (SCDR).
Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data
shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The
transfer of data to the transmit data shift register is synchronized with the bit rate clock (see
Figure 7-2). All data is transmitted least significant bit first. Upon completion of data transmission,
the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or
break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If
the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has
been sent, the TC bit will also be set. This will also generate an interrupt if the transmission
complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the
character being transmitted will be completed before the transmitter gives up control of the
TDO pin.
103



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