HC05 datasheet(108/232 Pages) MOTOROLA

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MOTOROLA

7-6

MC68HC05X16

Rev. 1

SERIAL COMMUNICATIONS INTERFACE

7.6.1

Idle line wake-up

In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle

is deﬁned as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems

using this type of wake-up must provide at least one character time of idle between messages to

wake up sleeping receivers, but must not allow any idle time between characters within a message.

7.6.2

Address mark wake-up

In address mark wake-up, the most signiﬁcant bit (MSB) in a character is used to indicate whether

it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address

character is received. Systems using this method for wake-up would set the MSB of the ﬁrst

character of each message and leave it clear for all other characters in the message. Idle periods

may be present within messages and no idle time is required between messages for this wake-up

method.

7.7

Receive data in (RDI)

Receive data is the serial data that is applied through the input line and the SCI to the internal bus.

The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred

to as the RT rate in Figure 7-4 and as the receiver clock in Figure 7-2.

The receiver clock generator is controlled by the baud rate register, as shown in Figure 7-1 and

Figure 7-2; however, the SCI is synchronized by the start bit, independent of the transmitter.

Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three

times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start),

as shown in Figure 7-5. The value of the bit is determined by voting logic which takes the value of

the majority of the samples. A noise ﬂag is set when all three samples on a valid start bit or data

bit or the stop bit do not agree.

7.8

Start bit detection

When the input (idle) line is detected low, it is tested for three more sample times (referred to as

the start edge veriﬁcation samples in Figure 7-4). If at least two of these three veriﬁcation samples

detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A

noise ﬂag is set if one of the three veriﬁcation samples detect a logic one, thus a valid start bit could

be assumed with a set noise ﬂag present.

If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros

for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start

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HC05 Datasheet(PDF) 108 Page - Motorola, Inc