HC05 datasheet(112/232 Pages) MOTOROLA

112 / 232 page

MOTOROLA

7-10

MC68HC05X16

Rev. 1

SERIAL COMMUNICATIONS INTERFACE

7.11

SCI registers

The SCI system is conﬁgured and controlled by ﬁve registers: SCDR, SCCR1, SCCR2, SCSR,

and BAUD.

7.11.1

Serial communications data register (SCDR)

The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts

as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it

is written. Figure 7-1 shows this register as two separate registers, RDR and TDR. The RDR

provides the interface from the receive shift register to the internal data bus and the TDR provides

the parallel interface from the internal data bus to the transmit shift register.

The receive data register is a read-only register containing the last byte of data received from the

shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status

SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as

shown in Figure 7-1. All data is received with the least signiﬁcant bit ﬁrst.

The transmit data register (TDR) is a write-only register containing the next byte of data to be

applied to the transmit shift register from the internal data bus. As long as the transmitter is

enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte

in the shift register has been transmitted).

The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as

shown in Figure 7-1. All data is received with the least signiﬁcant bit ﬁrst.

7.11.2

Serial communications control register 1 (SCCR1)

The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character

format, the receiver wake-up feature and the options to output the transmitter clocks for

synchronous transmissions.

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

SCI data (SCDR)

$0011

0000 0000

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

SCI control 1 (SCCR1)

$000E

WAKE CPOL

CPHA

LBCL

Undeﬁned

110

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