HC05 datasheet(115/232 Pages) MOTOROLA

Part #	HC05

Description	High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

PDF	232 Pages

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Manufacturer	MOTOROLA [Motorola, Inc]

Direct Link	http://www.freescale.com

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115 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

7-13

SERIAL COMMUNICATIONS INTERFACE

LBCL – Last bit clock

This bit allows the user to select whether the clock associated with the last data bit transmitted

(MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if

the LBCL bit is a logic one, and is not output if it is a logic zero.

The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by M-bit

(seeTable 7-2).

This bit should not be manipulated while the transmitter is enabled.

Figure 7-10 SCI data clock timing diagram (M=1)

Table 7-2 SCI clock on SCLK pin

Data format

M-bit

LBCL bit

Number of clocks on

SCLK pin

8 bit

9 bit

Idle or preceding

transmission

clock

Stop

Start

LSB

data

M = 1 (9 data bits)

Idle or next

LBCL bit controls last data clock

transmission

clock

Start

Stop

0123456

MSB

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

113

HC05 Datasheet(PDF) 115 Page - Motorola, Inc

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