HC05 datasheet(117/232 Pages) MOTOROLA

117 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

7-15

SERIAL COMMUNICATIONS INTERFACE

After loading the last byte in the serial communications data register and receiving the TDRE ﬂag,

the user should clear TE. Transmission of the last byte will then be completed and the line will go

idle.

1 (set)

–

Transmitter enabled.

0 (clear) –

Transmitter disabled.

RE — Receiver enable

1 (set)

–

Receiver enabled.

0 (clear) –

Receiver disabled.

When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,

OR, NF and FE) are inhibited.

RWU — Receiver wake-up

When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables

the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit

discussed above (in the SCCR1). When the RWU bit is set, no status ﬂags will be set. Flags which

were set previously will not be cleared when RWU is set.

If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)

consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is

set, RWU is cleared after receiving an address bit. The RDRF ﬂag will then be set and the address

byte stored in the receiver data register.

SBK — Send break

If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros

and then reverts to idle sending data. If SBK remains set, the transmitter will continually send

whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the

transmitter sends at least one high bit to guarantee recognition of a valid start bit.

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HC05 Datasheet(PDF) 117 Page - Motorola, Inc