HC05 datasheet(118/232 Pages) MOTOROLA

118 / 232 page

MOTOROLA

7-16

MC68HC05X16

Rev. 1

SERIAL COMMUNICATIONS INTERFACE

7.11.4

Serial communications status register (SCSR)

The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for

generation of the SCI system interrupt. In addition, a noise ﬂag bit and a framing error bit are also

contained in the SCSR.

TDRE — Transmit data register empty ﬂag

This bit is set when the contents of the transmit data register are transferred to the serial shift

transmit data register to clear the TDRE ﬂag.

If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial

communications data register will overwrite the previous value. The TDRE bit is cleared by

accessing the serial communications status register (with TDRE set) followed by writing to the

serial communications data register.

TC — Transmit complete ﬂag

This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data

in shift register, no preamble, no break). When TC is set the serial line will go idle (continuous

MARK). The TC bit is cleared by accessing the serial communications status register (with TC set)

followed by writing to the serial communications data register. It does not inhibit the transmitter

function in any way.

RDRF — Receive data register full ﬂag

This bit is set when the contents of the receiver serial shift register are transferred to the receiver

data register.

If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as

appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications

status register is accessed (with RDRF set) followed by a read of the serial communications data

IDLE — Idle line detected ﬂag

This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven

consecutive ‘1’s). This bit will not be set by the idle line condition when the RWU bit is set. This

allows a receiver that is not in the wake-up mode to detect the end of a message, detect the

preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by

accessing the serial communications status register (with IDLE set) followed by a read of the serial

communications data register. Once cleared, IDLE will not be set again until after RDRF has been

set, (i.e. until after the line has been active and becomes idle again).

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

SCI status (SCSR)

$0010

TDRE

RDRF

IDLE

1100 000u

116

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