 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HC05 Datasheet(PDF) 102 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
HC05 Datasheet(HTML) 102 Page - Motorola, Inc |
|
|
102 / 232 page  MOTOROLA 6-14 MC68HC05X16 Rev. 1 PROGRAMMABLE TIMER 6 Figure 6-4 Timer state timing diagram for output compare Figure 6-5 Timer state timing diagram for timer overflow Internal processor clock 16-bit counter $F456 $F457 $F458 $F459 Internal timer clocks T00 T01 T11 T10 $F457 CPU writes $F457 Output compare flag and TCMP1,2 Note: The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare. Output compare register Compare register latch (Note 2) (Note 1) (Note 1) Internal processor clock 16-bit counter $FFFF $0000 $0001 $0002 Internal timer clocks T00 T01 T11 T10 Note: The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by a read of the timer status register during the internal processor clock high time, followed by a read of the counter low register. Timer overflow flag 100 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
