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HC05 Datasheet(PDF) 167 Page - Motorola, Inc

Part # HC05
Description  High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
PDF  232 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

HC05 Datasheet(HTML) 167 Page - Motorola, Inc

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MC68HC05X16
Rev. 1
MOTOROLA
12-5
ELECTRICAL SPECIFICATIONS
12
12.4
Control timing
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (tcyc), this is the limiting
factor in determining the timer resolution.
(3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute
the capture interrupt service routine plus 24 tcyc.
(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute
the interrupt service routine plus 21 tcyc.
(5) At a temperature of 85
°C.
(6) Refer to Reliability Monitor Report (currrent quarterly issue) for current failure rate information.
Table 12-4 Control timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Oscillator frequency
MCAN module clock frequency
MCU bus frequency
fOSC
fCAN
fMCU
0
0
0
22
11
2.2
MHz
MHz
MHz
Cycle time (see Figure 10-1)tCYC
455
—
ns
Crystal oscillator start-up time (see Figure 10-1)tOXOV
—
100
ms
Stop recovery start-up time (crystal oscillator)
tILCH
100
ms
A/D converter stabilization time
tADON
500
µs
External RESET input pulse width
tRL
1.5
—
tCYC
Power-on RESET output pulse width (mask option)
4064 cycle
16 cycle
tPORL
tPORL
4064
16
—
—
tCYC
tCYC
Watchdog RESET output pulse width
tDOGL
1.5
—
tCYC
Watchdog time-out
tDOG
6144
7168
tCYC
EEPROM byte erase time
tERA
10
10
ms
EEPROM byte program time(1)
tPROG
10
10
ms
Timer (see Figure 12-1)
Resolution(2)
Input capture pulse width
Input capture pulse period
tRESL
tTH, tTL
tTLTL
4
125
—(3)
—
—
—
tCYC
ns
tCYC
Interrupt pulse width (edge-triggered)
tILIH
125
—
ns
Interrupt pulse period
tILIL
—(4)
—tCYC
OSC1 pulse width
tOH, tOL
90
—
ns
Write/erase endurance(5)(6)
—
10000
cycles
Data retention(5)(6)
—
10
years
Figure 12-1 Timer relationship
External
signal
(TCAP1,
TCAP2)
tTLTL
tTH
tTL
165



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