HC05 datasheet(151/232 Pages) MOTOROLA

151 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

11-3

CPU CORE AND INSTRUCTION SET

Half carry (H)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

Interrupt (I)

When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set,

the interrupt is latched and remains pending until the interrupt bit is cleared.

Negative (N)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was

negative.

Zero (Z)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was

zero.

Carry/borrow (C)

When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred

during the last arithmetic operation. This bit is also affected during bit test and branch instructions

and during shifts and rotates.

11.2

Instruction set

The MCU has a set of 62 basic instructions. They can be grouped into ﬁve different types as

follows:

–

Read/modify/write

–

Branch

–

Bit manipulation

–

Control

The following paragraphs brieﬂy explain each type. All the instructions within a given type are

presented in individual tables.

This MCU uses all the instructions available in the M146805 CMOS family plus one more: the

unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents

of the accumulator (A) and the index register (X). The high-order product is then stored in the index

instruction is shown in Table 11-1.

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HC05 Datasheet(PDF) 151 Page - Motorola, Inc