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HC05 Datasheet(PDF) 155 Page - Motorola, Inc |
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HC05 Datasheet(HTML) 155 Page - Motorola, Inc |
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155 / 232 page ![]() MC68HC05X16 Rev. 1 MOTOROLA 11-7 CPU CORE AND INSTRUCTION SET 11 Table 11-5 Read/modify/write instructions Addressing modes Inherent (A) Inherent (X) Direct Indexed (no offset) Indexed (8-bit offset) Function Mnemonic Increment INC 4C 1 3 5C 1 3 3C 2 5 7C 1 5 6C 2 6 Decrement DEC 4A 1 3 5A 1 3 3A 2 5 7A 1 5 6A 2 6 Clear CLR 4F 1 3 5F 1 3 3F 2 5 7F 1 5 6F 2 6 Complement COM 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 Negate (two’s complement) NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 Rotate left through carry ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 Rotate right through carry ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 Logical shift left LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 Logical shift right LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 Arithmetic shift right ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 Test for negative or zero TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5 Multiply MUL 42 1 11 Set bit n BSET n (n=0–7) 10+2•n 2 5 Clear bit n BCLR n (n=0–7) 11+2•n 2 5 Table 11-6 Control instructions Inherent addressing mode Function Mnemonic Opcode # Bytes # Cycles Transfer A to X TAX 97 1 2 Transfer X to A TXA 9F 1 2 Set carry bit SEC 99 1 2 Clear carry bit CLC 98 1 2 Set interrupt mask bit SEI 9B 1 2 Clear interrupt mask bit CLI 9A 1 2 Software interrupt SWI 83 1 10 Return from subroutine RTS 81 1 6 Return from interrupt RTI 80 1 9 Reset stack pointer RSP 9C 1 2 No-operation NOP 9D 1 2 Stop STOP 8E 1 2 Wait WAIT 8F 1 2 153 |
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