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HC05 Datasheet(PDF) 157 Page - Motorola, Inc |
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HC05 Datasheet(HTML) 157 Page - Motorola, Inc |
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157 / 232 page  MC68HC05X16 Rev. 1 MOTOROLA 11-9 CPU CORE AND INSTRUCTION SET 11 COM •• ◊◊ 1 CPX •• ◊◊◊ DEC •• ◊◊ • EOR •• ◊◊ • INC •• ◊◊ • JMP ••••• JSR ••••• LDA •• ◊◊ • LDX •• ◊◊ • LSL •• ◊◊◊ LSR •• 0 ◊◊ MUL 0 ••• 0 NEG •• ◊◊◊ NOP ••••• ORA •• ◊◊ • ROL •• ◊◊◊ ROR •• ◊◊◊ RSP ••••• RTI ????? RTS ••••• SBC •• ◊◊◊ SEC •••• 1 SEI • 1 ••• STA •• ◊◊ • STOP • 0 ••• STX •• ◊◊ • SUB •• ◊◊◊ SWI • 1 ••• TAX ••••• TST •• ◊◊ • TXA ••••• WAIT • 0 • • • Table 11-7 Instruction set (Continued) Mnemonic Addressing modes Condition codes INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C Condition code symbols H Half carry (from bit 3) ◊ Tested and set if true, cleared otherwise I Interrupt mask • Not affected N Negate (sign bit) ? Load CCR from stack Z Zero 0 Cleared C Carry/borrow 1 Set Not implemented Address mode abbreviations BS C Bit set/clear IMM Immediate BTB Bit test & branch IX Indexed (no offset) DIR Direct IX1 Indexed, 1 byte offset EXT Extended IX2 Indexed, 2 byte offset 155 |
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