HC05 datasheet(153/232 Pages) MOTOROLA

153 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

11-5

CPU CORE AND INSTRUCTION SET

Table 11-1 MUL instruction

Operation

X:A ¨ X*A

Description

Multiplies the eight bits in the index register by the eight

bits in the accumulator and places the 16-bit result in the

concatenated accumulator and index register.

Condition

codes

H : Cleared

I : Not affected

N : Not affected

Z : Not affected

C : Cleared

Source

MUL

Form

Addressing mode

Cycles

Bytes

Opcode

Inherent

$42

Table 11-2 Register/memory instructions

Addressing modes

Immediate

Direct

Extended

Indexed

(no

offset)

Indexed

(8-bit

offset)

Indexed

(16-bit

offset)

Function

Load A from memory

LDA

Load X from memory

LDX

Store A in memory

STA

Store X in memory

STX

Add memory to A

ADD

Add memory and carry to A

ADC

Subtract memory

SUB

Subtract memory from A

with borrow

SBC

AND memory with A

AND

OR memory with A

ORA

Exclusive OR memory with A

EOR

Arithmetic compare A

with memory

CMP

Arithmetic compare X

with memory

CPX

Bit test memory with A

(logical compare)

BIT

Jump unconditional

JMP

Jump to subroutine

JSR

151

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