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HC05 Datasheet(PDF) 156 Page - Motorola, Inc |
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HC05 Datasheet(HTML) 156 Page - Motorola, Inc |
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156 / 232 page  MOTOROLA 11-8 MC68HC05X16 Rev. 1 CPU CORE AND INSTRUCTION SET 11 Table 11-7 Instruction set Mnemonic Addressing modes Condition codes INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C ADC ◊ • ◊◊◊ ADD ◊ • ◊◊◊ AND •• ◊◊ • ASL •• ◊◊◊ ASR •• ◊◊◊ BCC ••••• BCLR ••••• BCS ••••• BEQ ••••• BHCC ••••• BHCS ••••• BHI ••••• BHS ••••• BIH ••••• BIL ••••• BIT •• ◊◊ • BLO ••••• BLS ••••• BMC ••••• BMI ••••• BMS ••••• BNE ••••• BPL ••••• BRA ••••• BRN ••••• BRCLR •••• ◊ BRSET •••• ◊ BSET ••••• BSR ••••• CLC •••• 0 CLI • 0 ••• CLR •• 0 1 • CMP • • ◊◊◊ Condition code symbols H Half carry (from bit 3) ◊ Tested and set if true, cleared otherwise I Interrupt mask • Not affected N Negate (sign bit) ? Load CCR from stack Z Zero 0 Cleared C Carry/borrow 1 Set Not implemented Address mode abbreviations BS C Bit set/clear IMM Immediate BTB Bit test & branch IX Indexed (no offset) DIR Direct IX1 Indexed, 1 byte offset EXT Extended IX2 Indexed, 2 byte offset 154 |
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