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AD9173 Datasheet(PDF) 118 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 118 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 118 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x45C
ILS_RES2
[7:0]
RES2
Reserved field 2. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
0x45D
ILS_CHECKSUM
[7:0]
FCHK0
Calculated link configuration checksum. This control
is paged by the LINK_PAGE control in Register
0x300. This signal must only be programmed while
the QBD is held in soft reset (Register 0x475, Bit 3),
and must not be changed during normal operation.
0x0
R/W
0x46C
LANE_DESKEW
7
ILD7
Interlane deskew status for Lane 7. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
6
ILD6
Interlane deskew status for Lane 6. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
5
ILD5
Interlane deskew status for Lane 5. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
4
ILD4
Interlane deskew status for Lane 4. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
3
ILD3
Interlane deskew status for Lane 3. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
2
ILD2
Interlane deskew status for Lane 2. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
1
ILD1
Interlane deskew status for Lane 1. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
0
ILD0
Interlane deskew status for Lane 0. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
0x46D
BAD_DISPARITY
7
BDE7
Bad disparity errors status for Lane 7. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
6
BDE6
Bad disparity errors status for Lane 6. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
5
BDE5
Bad disparity errors status for Lane 5. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.



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